A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

Manikandan, R.; Amrutur, Bharadwaj

doi:10.1016/j.mejo.2015.03.004

Cited by 20 publications

(5 citation statements)

References 41 publications

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“…Injection Current ence [12], [14], and [16]. Compared with work in reference [12], [14], the reference spur is reduced by almost 21 dB on the condition of near in-band phase noise performance, VCO gain and loop bandwidth. In [16], the reference spur is suppressed but at the price of large loop bandwidth and larger area.…”

Section: Conditionsmentioning

confidence: 89%

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A low reference spur phase-locked loop realized with dynamic current injection charge pump

2019

IEICE Electron. Express

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A dynamic current injection charge pump (DCI-CP) is proposed to obtain perfect dynamic current match in this paper. In the proposed DCI-CP, dynamic injection current which includes positive injection current and negative injection current is generated to compensate the dynamic current mismatch. To verify the proposed DCI-CP, a CPPLL is fabricated in SMIC 0.18-µm CMOS process. Measurement results show that it synthesizes frequency from 0.6 to 1.3 GHz with a supply voltage of 1.8 V, consuming 4.7 mW. Simulation results show the dynamic current mismatching of proposed DCI-CP is as low as 4 nA even in the worst case. The measurement reference spur achieves −74 dBc at 1.1 GHz oscillation frequency, of which the maximum and minimum reduction are 9 dB and 3 dB, respectively. The phase noise achieves −98.5 dBc/Hz @1 MHz offset. The core occupies a die area of 0.154 mm 2 totally.

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Section: Conditionsmentioning

confidence: 89%

“…In order to suppress the ripple, decreasing the loop bandwidth is an effective way [14,15]. Besides, many other attempts have also been tried to reduce reference spur in the past few years [16,17,18,19,20,21,22,23,24,25].…”

Section: Introductionmentioning

confidence: 99%

A low reference spur phase-locked loop realized with dynamic current injection charge pump

2019

IEICE Electron. Express

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“…To circumvent this problem, the charge pump was split into two branches, and an opamp was used as a buffer between the two branches [15]. This method of current steering was enhanced and improved, by using adaptive body bias tuning, and by reducing the threshold voltage of the p‐MOSFET [16]. Alternatively, the opamp was used in open‐loop configuration, and to eliminate the residual channel charges, dummy switches were included [17].…”

Section: Related Previous Workmentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Koithyar

Ramesh

2020

IET Circuits, Devices & Systems

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In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

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“…However, the finite current step of the signed counter leads to the difficulty in achieving exact matching of the CP current. The auxiliary loop-based calibration method [23] uses successive approximation register (SAR) and DAC at the cost of taking a long time to return to the lock mode. On the other hand, an adaptive body bias technique [24,25] using a number of resistances adjusts the threshold voltage of MOS transistors to reduces current variation caused by the process variation.…”

Section: Introductionmentioning

confidence: 99%

A high swing charge pump with current mismatch reduction for PLL applications

Chen

Han

Wang

2021

IEICE Electron. Express

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A charge pump (CP) is widely used in modern phase-locked loop (PLL) implementations. The CP current mismatch is a dominant source of static phase offset and reference spur in the PLL output signals. In this paper, a novel CP with small current mismatch characteristic over a wide output voltage range is proposed. The specially designed dual compensation circuits use the unity-gain feedback operational amplifier and current mirrors to reduce the current mismatch when the output voltage is closed to the supply voltage (V DD) or ground (GND). And the additional feedback transistors are used to reduce the impact from the channel length modulation effect. Post-layout simulation results demonstrate that the output current of the proposed CP in a 40 nm CMOS technology is 115 μA. Moreover, the current mismatch is less than 0.97 μA or 0.84% over the output voltage range from 0.04 to 1.07 V covering more than 93.6% of the 1.1 V supply. Thus, the proposed CP maximizes the dynamic range, and reduces the phase offset and reference spur of CP-PLLs.

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A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

Cited by 20 publications

References 41 publications

A low reference spur phase-locked loop realized with dynamic current injection charge pump

A low reference spur phase-locked loop realized with dynamic current injection charge pump

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

A high swing charge pump with current mismatch reduction for PLL applications

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