A Wireless Network-on-Chip Design for Multicore Platforms

Wang, Chifeng; Hu, Wen-Hsiang; Bagherzadeh, Nader

doi:10.1109/pdp.2011.37

Cited by 80 publications

(48 citation statements)

References 24 publications

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“…Another work proposing long-distance single-hop wireless communications in a NoC is presented by Wang et al [23]. To analyze the proposed network, an architecture with 100 cores split into 4 sub-networks was simulated in a System-C-based simulator.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

2015

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Background: Parallel processing in the era of many-core processors demands high-performance networks-on-chip and parallel communication based on intra-chip message passing. In this context, wireless networks-on-chip (WiNoCs) emerge to improve inter-core communication, bringing high bandwidth and low power consumption. In order to increase application performance, WiNoCs can support single-hop or multi-hop communication. The main issue is related to the performance of each communication architecture in the face of different parallel workloads. For this reason, the goal of this work is to evaluate and compare single-and multi-hop WiNoC architectures using parallel applications. Methods: The methodology is based on simulations done using the well-known simulator Network Simulator 2 (NS-2) and applications from NAS Parallel Benchmarks (NPB). The WiNoC architectures are based on 2-D mesh topology and ultra wide band (UWB) radio technology. The inter-core transmission is evaluated concerning unicast communication (1:1 and N:1) and broadcast communication (1:N and N:N). This work has, as contribution to the state-of-the-art, the evaluation of both WiNoC designs (single-and multi-hop architectures) with parallel applications. Results: Based on our results, the single-hop architecture has lower communication delay than the multi-hop version, and for some workloads, there were no packet losses. However, to achieve high-performance communication, the single-hop architecture consumed 63.12 J for the 256-node network, versus 0.22 J consumed by the multi-hop version. Conclusions: Although single-hop WiNoCs reduce network bottlenecks and increase communication parallelism, they are recommended when energy consumption is not a critical factor.

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Section: Related Workmentioning

confidence: 99%

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

2015

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“…For a packet whose source node and destination node are located in the same block, there's no need to use the wireless links, thus the packet will be sent from source to destination by wired links using XY routing. For a packet whose source node and destination node are from different blocks, the factor δ for congestion control is set to avoid excessive use of wireless links and produce hotspot [7]. The routing decision algorithm combing XY with TXY is adopted in our proposed architecture to avoid deadlocks.…”

Section: Communication Mechanism Of Vt-awinocmentioning

confidence: 99%

“…In [7], performance of WiNoC architecture based on conventional wired 2D Mesh NoC architecture called NePA has been shown to improve by a hybrid mechanism taking advantage of both wired and wireless communications (denoted as NePA-WiNoC). The every subnet will be greater and easier to become congested with the network scale expansion.…”

Section: Introductionmentioning

confidence: 99%

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

Yong-liang

et al. 2015

IEICE Electron. Express

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In view of the high energy consumption and latency problem due to multi-hop wired links between distant cores of traditional large-scale Network-on-Chip, a virtual torus-based adaptive wireless NoC architecture has been proposed when analyzing the existing several wireless NoC architectures. By not only adopting the automatic detection and dynamic bandwidth allocation mechanism to hot wireless link based on the sensing parameter for improved congestion measurement, but also designing the Dynamic Allocation Control Circuit Module (DACCM) for transmitter, the intra-chip topology and link bandwidth could be adaptively adjusted as different traffic patterns. Experimental results show that the proposed architecture has more significant latency improvement and energy saving under different traffic patterns or real application such benchmark as FFT.

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“…Current WNoC architectures fall into two categories: single hop wireless NoC with long range onchip wireless data links [9,10], and multi-hop wireless NoC with short range on-chip wireless data links and larger number of wireless routers [8].…”

Section: Introductionmentioning

confidence: 99%

“…The concept of subnet was first introduced in Small World WNoC [9], where nodes in a local subnet is wire linked and each subnet communicates with other subnets through a hub. This idea is inherited in Hybrid Mesh WNoC [10] where a traditional 2D Mesh is divided into several subnets, and each subnet has a wireless node in the center that allows this subnet to directly communicate with other subnets wirelessly. On the other hand, the multi-hop wireless NoC architectures [8], due to their higher number of wireless routers, can reduce the competition at each wireless router, but suffer from great power consumption and require large chip area.…”

Section: Introductionmentioning

confidence: 99%

On an Overlaid Hybrid Wire/Wireless Interconnection Architecture for Network-on-chip

Wang¹,

Guo²,

Lv³

et al. 2014

IJACSA

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Abstract-Network-on-Chip (NoC) built upon metal low-k interconnect wires, are to meet the ever stringent performance requirements in the future technology nodes. In response to this interconnection crisis, the wireless network-on-chip (WNoC), enabled by the availability of miniaturized on-chip antennas and transceivers, is envisioned one of the most revolutionary promising approach alternatives. In this paper, we present a new WNoC architecture with a layered topology, where a metal/low-k based wired network is partitioned into several subnetworks, and these subnetworks are connected through a wireless network that is overlaid on top of them. Due to limited transmission range, the wireless nodes in the wireless network actually communicate with each other in a multiple-hop fashion. As a large volume of traffic will go through the wireless nodes, a contention avoidance routing algorithm is adopted. In addition, two virtual channels have been introduced into the wireless router design to avoid any possible deadlocks that otherwise may occur. Experiment results have shown that throughput of the proposed architecture, on average, is about 20% higher than that of the existing WNoC architectures. And delay of the proposed architecture is about 30% less than the existing WNoC architectures.

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A Wireless Network-on-Chip Design for Multicore Platforms

Cited by 80 publications

References 24 publications

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

On an Overlaid Hybrid Wire/Wireless Interconnection Architecture for Network-on-chip

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