A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

Abstract

A completely integrated, WiMedia/MBOA-compliant [1] RF transceiver for Ultra-Wideband (UWB) data communication in the 3 to 5GHz band is presented. It is designed in 0.13µm standard CMOS technology for a single supply voltage of 1.5V. The measured noise figure (NF) of 3.6 to 4.1dB over all three bands is significantly better (2 to 4dB) than existing CMOS [2] or BiCMOS SiGe [3] receive chains, and comparable to the BiCMOS SiGe receiver described in [4]. On the transmit side, an improvement in P 1dB of 15dB compared to [2] is achieved, supporting an EVM of -28dB up to -4dBm output power. This output power level is required to support realistic external losses.The block diagram of the direct conversion transceiver chip is shown in Fig. 6.5.1. The fully differential receiver includes an LNA with high-and low-gain modes and a programmable-gain amplifier (PGA) with 4 gain steps to enable optimum receive performance for different signal strengths and interferer scenarios [5]. The amplifiers are followed by a Gilbert-type down-conversion mixer, which generates quadrature (I and Q) outputs. It is based on a class-AB voltage-to-current converter, a Gilbert Quad, and a load that implements both a current-to-voltage converter and a low-noise filter used to suppress large out-of-band interferers. The position of the filter poles (around 500MHz) can be calibrated digitally by tuning filter capacitors, thus achieving good transition-band and stop-band accuracy in the presence of process variations. The analog I/Q chip interface is driven by an output buffer with a bandwidth of 1GHz to enable characterization of all receive chain impairments.On the TX side the baseband I/Q analog input signal is converted to a current by a highly linear voltage-to-current converter and fed into Gilbert-type folded upconverting mixers. To reduce the LO leakage caused by dc offset in the mixer stage, a compensation DAC is added and controlled by a serial interface bus. The differential output signal of the mixer is converted to single ended, followed by a programmable gain stage and an integrated 3-stage power amplifier (PA). The 3 required coils in the PA are realized by stacked inductors. Gain-switching is implemented by a capacitive divider with a switchable divider ratio, yielding a variable gain range of 30dB with a resolution of 1dB for high-gain settings. A power detector followed by an ADC with 6b resolution is implemented to measure the output voltage of the PA. Taking into account some back-off due to external losses, antenna and impedance mismatch, this scheme enables cost-efficient control of the actual output power to fulfill TX emission-mask requirements without external components. Figure 6.5.2 shows the block diagram of the LO generation. To generate the three required LO frequencies of 3.432, 3.960 and 4.488GHz with minimal transition time when hopping, an openloop topology is required.The principle idea is to add or subtract a low frequency (±264MHz or -792MHz) from a fixed frequency of 4.224GHz. The proposed implementation includ...

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