A Wideband Frequency Divider With Programmable Odd/Even Division Factors and Quadrature/Symmetrical Outputs

Rezaei-Hosseinabadi, Nasrin; Dehghani, Rasoul; Khajehoddin, S. Ali; Moez, Kambiz

doi:10.1109/tcsi.2020.2968181

Cited by 7 publications

(2 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, clock multiplication from one clean reference is preferred. Elkholy et al reported a multi-output all-digital clock generator based on open-loop delta-sigma (∆Σ) fractional dividers [5], and there are high-performance dividers that can potentially be implemented for clock multiplication [6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

et al. 2023

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 99%

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

et al. 2023

View full text Add to dashboard Cite

“…Also, a divide-by-2 frequency divider can be used to generate local oscillation (LO) signals for multistandard cellular transceivers. 14 An inductor less divide-by-5 ILFD was presented in Rezaei-Hosseinabadi et al 15 The fourth and sixth harmonics of the output signal were generated by the circuit nonlinearities, and these harmonics are mixed with the injection frequency to generate the intermodulation components. These components were made equal to the output frequency of the divider in a locked condition, and hence, we get a stabilized divide-by-5 signal.…”

Section: Introductionmentioning

confidence: 99%

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

Maity

Jana

Som

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents power and area optimized, high-speed metal-oxidesemiconductor (MOS) current mode logic (MCML)-based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide-by-2 frequency divider has been realized in a 180-nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst-case process corner with a maximum power dissipation of 1.715 mW under 1.8-V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 Â 0.09 mm 2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX-OR gates are used to design a divide-by-5 frequency divider that is also realized in 180-nm CMOS process technology. The postlayout simulation results show that the proposed divide-by-5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst-case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8-V supply. It occupies a 0.166 Â 0.116 mm 2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

show abstract

A Divide-By-5 Pre-scaler Design Approach for 5G Applications

Maity

Kundu

Jana

2021

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

A Wideband Frequency Divider With Programmable Odd/Even Division Factors and Quadrature/Symmetrical Outputs

Cited by 7 publications

References 19 publications

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

A Divide-By-5 Pre-scaler Design Approach for 5G Applications

Contact Info

Product

Resources

About