A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process

Palomeque-Mangut, David; Rodríguez-Vázquez, Á.; Delgado‐Restituto, Manuel

doi:10.1109/lascas53948.2022.9789044

Cited by 3 publications

(3 citation statements)

References 10 publications

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“…4 for simplicity-, slides the voltage levels of the digital control signals of the H-bridge from the 1.8 V domain to (1) V in , in the case of S N,1−2 ; and (2) V B,4 -V DDH in the case of S P,1−2 . This is done by means of floating level shifters [18], [30].…”

Section: B Neural Stimulator Front-endmentioning

confidence: 99%

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Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process

Palomeque-Mangut

Rodríguez-Vázquez

Delgado‐Restituto

2022

2022 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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This paper describes a neural stimulator with 4 × VDD compliance voltage, delivering up to 2.08 mA, and implemented in a standard 180 nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. The system has been fabricated, occupying an active area of 2.34 mm 2 . The circuit has been experimentally tested by connecting it to a custom µelectrode array which was immersed into a phosphate-buffered saline solution.

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Section: B Neural Stimulator Front-endmentioning

confidence: 99%

“…Neural stimulators are often combined with a neural recording section for adapting the stimulation on the tissue, thus resulting in a closed-loop architecture or neuromodulator. Besides, neural implants are often supplied by a Wireless Power and Data Transfer (WPDT) system to avoid the use of wires [15]- [18]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process

Palomeque-Mangut

Rodríguez-Vázquez

Delgado‐Restituto

2022

2022 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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“…Maeng et al 20 present n‐ and p‐type periodically refreshed capacitive floating LS, which can generate a floating signal without additional bias voltage, and all coupling capacitors can be simultaneously refreshed. In addition, based on a periodically‐refreshed charge pump circuit, Palomeque‐Mangut et al 21 exhibit a high‐voltage floating LS, which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing. Wang et al 22 show a multi‐function ultra‐low‐voltage LS with re‐configurable logic with embedded time‐borrowing latch.…”

Section: Introductionmentioning

confidence: 99%

An energy‐efficient level shifter based on a differential cascade voltage switch structure

Zhang

Liu

et al. 2022

Circuit Theory & Apps

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Based on differential cascade voltage switch architecture, this paper proposes a level shifter with optimized energy consumption, constructed by stacking diode‐connected NMOS and PMOS transistors and splitting input signals of the two output stages. Eventually, the overlap time of input signals of the two output stages has been reduced, during which there is a considerable short‐current from high voltage source to ground. When implemented in a 110 nm CMOS process, post‐layout netlist simulations show that the proposed level shifter exhibits a 2.31 ns switching delay and 819 fJ energy consumption when converting a 1.5 V input signal into 4.5 V with 10 MHz operational frequency and 15 fF output load.

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A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

Palomeque-Mangut

Rodríguez-Vázquez

Delgado‐Restituto

2022

Sensors

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This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

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A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process

Cited by 3 publications

References 10 publications

Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process

Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process

An energy‐efficient level shifter based on a differential cascade voltage switch structure

A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

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