A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

Tsai, Chih‐Wei; Chiu, Yu‐Ting; Tu, Yo-Hao; Cheng, Kuo-Hsing

doi:10.1109/tvlsi.2021.3098171

Cited by 7 publications

(3 citation statements)

References 17 publications

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“…In order to verify the proposed RVCO design methodology, RVCOs oscillating at the maximum clock rate (3.2 GHz) of DDR5 applications [25] in 40-nm and 7-nm technologies are produced. The target control voltage range is set to 75% and 85% of the nominal supply voltage, and the desired number of phases is set to 4 for the quadrature clock generation.…”

Section: Case Study: Ddr5mentioning

confidence: 99%

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

et al. 2023

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This paper presents a design automation methodology for ring voltage-controlled oscillators (RVCOs) with their realistic and physical characteristics captured. With multiple sets of input constraints such as target frequency, phase noise, and control voltage range, the proposed algorithm automatically finds the design candidates that satisfy the target constraints, by running iterative post-layout simulations with auto-generated layouts and testbenches. The number of post-layout simulations is significantly reduced by the backtracking algorithm that observes the simulation results and determines the search direction. The proposed algorithm is applied to generate RVCOs in 40-nm planar and 7-nm FinFET technologies for DDR5 applications, and it turns out the proposed methodology produces sets of design parameters that meet the target specification in multiple technologies.

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Section: Case Study: Ddr5mentioning

confidence: 99%

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

et al. 2023

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“…Digitizing circuits beneficially reduces design time. A time-to-digital converter (TDC) is a key component widely used in digital systems and circuits, such as light detection and ranging (LiDAR) system, all-digital phase locked loop (ADPLL), all-digital delay locked loop (ADDLL), etc [ 1,2,3].…”

Section: Introductionmentioning

confidence: 99%

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display

Hong,

Lo,

Shen

et al. 2023

Analog Integr Circ Sig Process

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This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in five clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal.Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking.Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm 2 .

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“…Compared to closed-loop DLLs, open-loop DLLs have shorter lock times because the SMD only measures phase shift once and eliminates phase differences in subsequent cycles. However, the open-loop structure lacks dynamic tracking capability and may lose synchronization after phase tracking [12]. The addition of high-performance digital-to-analog converters (ADCs) increases design difficulty and inevitably increases power consumption and area.…”

Section: Introductionmentioning

confidence: 99%

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

et al. 2023

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This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

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A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

Cited by 7 publications

References 17 publications

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

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