A Weighted Motion Compensation Interpolation Method for Improving Side Information in Distributed Video Coding

Zhang, Dengyin; Ji, Ying; Wang, Xue Mei

doi:10.4028/www.scientific.net/amm.519-520.670

Cited by 1 publication

(2 citation statements)

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“…The motion vector of all overlapping blocks present in the corresponding frames must be stored in a memory block for further processing and its architecture is given in Figure 7. The motion vector memory block is used to store the calculated motion vectors from the SAD data through compare and compensate The modules for estimating forward motion, bidirectional motion and smoothing spatial motion are the same as those in the original algorithm [21] with modification of motion compensation architecture with counter controlled registers instead of RAM controlled. The novel architecture used to implement the motion compensation through interpolation [21] is given in Figure 8.…”

Section: Motion Correctionmentioning

confidence: 99%

“…The motion vector memory block is used to store the calculated motion vectors from the SAD data through compare and compensate The modules for estimating forward motion, bidirectional motion and smoothing spatial motion are the same as those in the original algorithm [21] with modification of motion compensation architecture with counter controlled registers instead of RAM controlled. The novel architecture used to implement the motion compensation through interpolation [21] is given in Figure 8. The motion vectors obtained are then stored into another temporary memory which are then used for compensating the motion through interpolation array to generate the corrected motion vector.…”

Section: Motion Correctionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient reconfigurable architecture for moving object detection with motion compensation

Sridevi¹,

Meenakshi²

2021

IJEECS

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The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference and adder blocks designed using kogge-stone adder which helps in improving the speed of the architecture. The controller block is designed by finite state machine model used for synchronization of all the operations. Further, the comparator and compensation blocks are optimized by using basic logical elements and the Kogge-stone adder. Finally, the proposed architecture is implemented on Zynq Z7-10 field-programmable gate array (FPGA) and simulated using System Generator tool for real time traffic signal. The hardware and software parameters are compared with the existing techniques which shows that the proposed architecture is efficient than existing methods of design.

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Section: Motion Correctionmentioning

confidence: 99%

Section: Motion Correctionmentioning

confidence: 99%