A Web-CAD methodology for IP-core analysis and simulation

Fin, Alessandro; Fummi, Franco

doi:10.1145/337292.337590

Cited by 18 publications

(11 citation statements)

References 6 publications

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“…Researchers proposed cryptographic techniques (Silva andKatz 1995, Hauck andKnoll 1998) and simulation to take place on the manufacturer site (Fin and Fummi 2000). However, these approaches are either platform dependent, hard to maintain or do not support design by multiple components from different vendors.…”

Section: Distributed Problem-solving Approachesmentioning

confidence: 99%

Integrating vendors into cooperative design practices

Eskil

Sticklen

2009

CoDesign

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This paper describes a new approach to cooperative design using distributed, offthe-shelf design components. The ultimate goal is to enable assemblers to rapidly design their products and perform simulations using parts that are offered by a global network of suppliers. The obvious way to realise this goal would be to transfer desired component models to the client computer. However, in order to protect proprietary data, manufacturers are reluctant to share their design models without non-disclosure agreements, which can take in the order of months to put in place. Due to bandwidth limitations, it is also impractical to keep the models at the manufacturer site and do simulations by simple message passing. To deal with these impediments in e-commerce the modular distributed modelling (MDM) methodology is leveraged, which enables transfer of component models while hiding proprietary implementation details. MDM methodology with routine design (RD) methods are augmented to realise a platform (RD-MDM) that enables automatic selection of secured off-the-shelf design components over the Internet, integration of these components in an assembly, running simulations for design testing and publishing the approved product model as a secured MDM agent. This paper demonstrates the capabilities of the RD-MDM platform on a fuel cell-battery hybrid vehicle design example.

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Section: Distributed Problem-solving Approachesmentioning

confidence: 99%

Integrating vendors into cooperative design practices

Eskil

Sticklen

2009

CoDesign

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“…idently, while most commonly found software piracy is illegal redistribution [2,8], recent legal disputes involve CAD tools and algorithms are mainly on the misuse. Furthermore, the collaborated web-based design frameworks [3] make CAD tools more vulnerable than ever to unauthorized misuse.…”

Section: Introductionmentioning

confidence: 99%

VLSI CAD tool protection by birthmarking design solutions

Lin

Srivastava

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem P and a solution S, we want to be able to determine whether S is obtained by a particular tool or algorithm.We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution's quality. The post-processing technique balances the level of protection and design quality.We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool's performance.

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“…functionalities, testa- bility, performances, have to be evaluated before including it into the final design. Previously defined techniques [2,6,7,9] present alternative methodologies for allowing a design team to evaluate different IPs integrations into the final design without violating the IPs of the core provider. The goal of the technique presented in this paper is to integrate these functionality evaluation methodologies with a testability evaluation framework.…”

Section: Introductionmentioning

confidence: 99%

Protected IP-core test generation

Fin¹,

Fummi²

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. IPs are usually provided with their own test patterns that can be used only by applying design for testability techniques onto the chip. Whenever physical faults must be detected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test generation on faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. Finally, remote simulation can be also performed locally to avoid bandwidth bottleneck and the test generation process can be indifferently applied at lower abstraction levels such as RT and gate.

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A Web-CAD methodology for IP-core analysis and simulation

Cited by 18 publications

References 6 publications

Integrating vendors into cooperative design practices

Integrating vendors into cooperative design practices

VLSI CAD tool protection by birthmarking design solutions

Protected IP-core test generation

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