A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques

Yoo, Seongwoo; Hung, Shih-Chang; Yoo, Sang-Min

doi:10.1109/jssc.2019.2904209

Cited by 41 publications

(18 citation statements)

References 21 publications

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“…The figures of merit are, as for typical DPD evaluations, the in-band performance in terms of EVM and the out-of-band performance in terms of the adjacent channel power ratio (ACPR). The SNDPD is validated with two quadrature capacitive RF-DAC designs: a capacitive RF-DAC-based digital PA (DPA) [21] and a wideband low-noise quadrature capacitive RF-DAC, similar to [22].…”

Section: Measurement Results Of the Supply Network Dpdmentioning

confidence: 99%

“…1. Capacitive RF-DACs can be implemented as polar, quadrature, multiphase, or even as hybrid IQ transmitters [17]- [22], [30]- [32].…”

Section: Capacitive Rf-dacmentioning

confidence: 99%

“…The capacitive RF-DAC combines high linearity over a wide frequency range with high power efficiency [18]. Moreover, dedicated architectures can provide enough signal gain to omit an additional conventional RF-PA [21], [22].…”

mentioning

confidence: 99%

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A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

Trampitsch

Kalcher²,

Enzinger³

et al. 2021

IEEE Trans. Microwave Theory Techn.

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This article presents a novel digital predistortion (DPD) approach to compensate for nonlinear dynamic distortions caused by the supply network of capacitive radio frequency digital-to-analog converters (RF-DACs). The developed DPD concept recreates the voltage distortion on the RF-DAC's supply network and modulates the input signal such that the effects on the output signal of the RF-DAC are canceled. In contrast to conventional DPD approaches such as pruned Volterra series or memory polynomials, the complexity of the proposed concept is reduced to a feasible level, allowing for implementation in integrated circuits. Furthermore, the derived DPD model allows to use linear estimation algorithms for coefficient training. The presented DPD is demonstrated by measurements of two different capacitive RF-DAC designs and compared with conventional DPD approaches. EVM and adjacent channel power ratio (ACPR) can be improved by up to 6 and 7 dB, respectively, outperforming conventional approaches. Index Terms-Digital predistortion (DPD), memory effects, memory polynomial (MP), power amplifier (PA), radio frequency digital-to-analog converter (RF-DAC), switched-capacitor power amplifier (SCPA), Volterra series. I. INTRODUCTION T HE demand for high data rates, robust transmissions, and power efficiency poses stringent requirements on the design of integrated wireless transceiver systems. Increasing the data rate, while simultaneously providing a reliable and power-efficient transmission, is closely related to the linearity of the communication systems. In radio frequency (RF) wireless communication transmitters, the key component in terms of linearity and Manuscript

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Section: Measurement Results Of the Supply Network Dpdmentioning

confidence: 99%

“…1. Capacitive RF-DACs can be implemented as polar, quadrature, multiphase, or even as hybrid IQ transmitters [17]- [22], [30]- [32].…”

Section: Capacitive Rf-dacmentioning

confidence: 99%

See 1 more Smart Citation

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

Trampitsch

Kalcher²,

Enzinger³

et al. 2021

IEEE Trans. Microwave Theory Techn.

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“…Compared with analog PAs, digital PAs (DPAs) [7]- [16] exhibit enhanced efficiency and medium output power. Recently, to implement watt-level DPAs, topologies of voltage-combining [17], [18] and currentcombining [19]- [21] are developed. However, compact wattlevel CMOS DPAs with merits of wideband, high efficiency, and low supply remain challenges.…”

Section: Introductionmentioning

confidence: 99%

1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

Wang

Qian

Yang

et al. 2021

IEEE Microw. Wireless Compon. Lett.

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In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2-2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power (P avg) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with P avg of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.

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“…Switched-capacitor power amplifier (SCPA) has become a popular PA concept in the RF IC domain, since the structure is CMOS friendly, i.e., easy to integrate, and it provides high linearity [1]. Until now SCPAs have been demonstrated at RF frequencies below 5 GHz [2]- [5], and there has been some doubts about the feasibility of this concept at higher frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs

Saleem

Stadius

Kosunen

et al. 2020

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Switched-capacitor power amplifier has gained popularity within the radio frequency integrated circuit community, since it is CMOS compatible offering high integration density and good performance particularly in terms of linearity. In this paper we present a study on the use of switched-capacitor power amplifier at millimeter-wave frequency range. We identify the major design challenges in this paper, and demonstrate the feasibility of switched-capacitor power amplifier with a 30-GHz design case. Our analysis describes the effects of power amplifier device parasitics and their contribution to dynamic power consumption, revealing that these are a major factor in degradation of switched capacitor power amplifier efficiency at millimeter waves. Two circuits, one for 3 GHz and the other for 30 GHz, were designed and simulated with 28-nm bulk CMOS technology. At 3 GHz, the designed switched capacitor power amplifier structure with 6-bit resolution features maximum output power of 19.4 dBm and efficiency of 59% whereas the output power of 18.6 dBm with 21% efficiency is achieved at 30 GHz. The switched-capacitor power amplifier preserves its good linearity at higher frequencies as well, and our design demonstrates an adjacent channel leackage ratio of-34.4 dB at 30 GHz for a 100-MHz OFDM-modulated signal.

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A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques

Cited by 41 publications

References 21 publications

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs

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