A wafer-scale 170000-gate FFT processor with built-in test circuits

Yamashita, Koichi; Kanasugi, Akinori; Hijiya, S.; Goto, G.; Matsumura, Nobutake; Shirato, Takafumi

doi:10.1109/4.993

Cited by 44 publications

(9 citation statements)

References 13 publications

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“…This paper deals with an architecture with constant geometry for the computation of the complex N point FFT [7]. This basic architecture consists of lo@ stages (or columns), each stage is made of N f 2 basic cells ( Figure (1)).…”

Section: Basic Principlesmentioning

confidence: 99%

“…The basic step of a butterfly computation to transform the complex inputs xu and xb ( Figure (2)) in an N-point FlT can be written as xuo=xu + y x x b , xbo=m -y x r b , y o = y . where y = = is the complex twiddle factor [7]. Inputloutput signals and all operations on them are executed over mod(m); it will be assumed that all signals are in integer format (the extension to complex fixed point numbers is not difficult, but it considerably adds to the complexity of the presentation).…”

Section: Basic Principlesmentioning

confidence: 99%

“…Connections between cells in adjacent stages is as in the constant geometry architecture of[7]. Prior to presenting the testability analysis a topological equivalence must be established between a FFT array (such as shown inFigure (1)) and the so-called linear (one-dimensional) array (Figure (3)).…”

mentioning

confidence: 99%

“…(6) The combinational fault model assumes at most a single unrestricted faulty cell [8]. A component-level fault model is dealt with in Section (7). Each component (adder or multiplier) is assumed to be satisfying any of the criteria for C-testability given in [5].…”

mentioning

confidence: 99%

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Testing constant-geometry FFT arrays for wafer scale integration

Salinas

Feng

Lombardi

1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration

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This paper presents new approaches for testing constant-geometry WSI array architectures used in the computation of the complex N-point Fast Fourier Transform under a single combmtional fault model. Initially, an unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C-as constant) of the number of cells in the FFT architeclure. The second proposed method is based on a testing process whose complexity is linear w i t h respect to the number of stages (columns) of the FFT may. No additional hardware is required in this case. A component-level fault model is also proposed and analyzed.

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Section: Basic Principlesmentioning

confidence: 99%

Section: Basic Principlesmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Testing constant-geometry FFT arrays for wafer scale integration

Salinas

Feng

Lombardi

1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration

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“…The 2-point butterfly module then can be constructed with four identical multiply-subtract-add (MSA) modules [16,17,18] as shown in Fig. 8.…”

Section: A Review Of Fft Butterfly Networkmentioning

confidence: 99%

Enhancing delay fault testability for iterative logic arrays

Yeh

2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings.

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Iterative Logic Arrays are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. Therefore, in order to improve the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as the sequential fault models and the delay fault models should also be considered. Therefore, delay fault testability conditions are proposed for iterative logic arrays (ILAs) in this paper. Our approach applies to ILA's with an arbitrary dimension, e.g., linear and mesh-connected ILAs, etc. Moreover, it can also be applied to various other connection types, e.g., butterfly-connected and shuffle-connected ones. A designfor-testability approach is used to make these arrays delay fault testable based on the proposed testability conditions. To illustrate our approach, we give a delay fault testable FFT processor as an example and show that an overhead of no more than 5% is sufficient to make it C-testable. It requires only 128 2-pattern tests to achieve 100% cell-delay-fault coverage regardless of the word length and the computation points of the FFT processor. Our approaches also guarantee that the test set is easy to generate, and the corresponding BIST structure requires smaller hardware overhead and has a more regular structure.

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Redundancy design of a wafer scale and high-speed FFT processor

Tomabechi

Kanazawa

1997

Syst. Comp. Jpn.

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A wafer-scale 170000-gate FFT processor with built-in test circuits

Cited by 44 publications

References 13 publications

Testing constant-geometry FFT arrays for wafer scale integration

Testing constant-geometry FFT arrays for wafer scale integration

Enhancing delay fault testability for iterative logic arrays

Redundancy design of a wafer scale and high-speed FFT processor

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