A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

Abbas, Zia; Mastrandrea, Antonio; Olivieri, Mauro

doi:10.1109/tvlsi.2013.2294550

Cited by 28 publications

(9 citation statements)

References 26 publications

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“…Similarly, leakage power shows several order of increment in WCO. Notably, leakage currents, depend on the device parameters like doping profile, gate oxide thickness, channel dimensions, etc., as well as on temperature, are substantially affected by the values of the logic signals at the input of the cell, and the influence of the process and operating variations can be different for different input combinations [31]. Therefore, the optimization has been carried out for all possible input combinations in the full adder [32].…”

Section: Design Goal Setupmentioning

confidence: 99%

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

2016

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We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

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Section: Design Goal Setupmentioning

confidence: 99%

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

2016

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“…As an example, in the two-input NOR cell, the optimization was carried out for all delay arcs with all possible input-output combinations, including rising and falling output transitions, as well as for all possible input combinations influencing leakage power, as summarized in Table I. It may not be a good practice to optimize a standard cell only for one input combination of leakage even if it corresponds to maximum leakage or maximum propagation delay, because such circuit sizing considering only one particular input combination may lead to failure of the circuit for other combinations [18]. All delays have been calculated at 2 fF load capacitance (10× minimum input capacitance in the target technology).…”

Section: Performance and Performance Specificationmentioning

confidence: 99%

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

Abbas

Olivieri

2015

Circuit Theory & Apps

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Process variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [À40°C, 125°C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)-level Monte Carlo analysis confirmed the estimated yield of the obtained circuits.slow corners for such devices. However, digital corners account for global variation, not including local variations effects, which are critical in the present scenario [24]. Also, digital corners are not design-specific, which is necessary to determine the impact of variation. Such characteristics limit the accuracy of the digital corners and cannot be considered as accurate indicators of performance variation bounds [25]. In order to achieve effective variation-aware design, we must thoughtfully account both the statistical inter-die and intra-die variations, and the operating condition fluctuations.As a result, statistical optimization for yield has become a crucial task in IC design, and because the specifications of an IC usually have challenging trade-offs, requiring multidimensional, multiobjective optimization, the role of mathematical techniques for circuit analysis and yield optimization has become essential to obtain solutions that satisfy the requested performance in the least time effort [6][7][8][9]14]. Transistor level designs like standard cells are most susceptible to parametric yield issues caused by process/operating variations [10,11,13,16,17,23] and are the scope of this work. Several design time transistor sizing algorithms have been proposed in literature to optimize the delay and/or power variations. In [27], authors report an approach for the variation-tolerant gate sizing incorporating statistical timing model. The proposed approach formulates a statistical objective and timing constraints and solves the resulting nonlinear optimization. However, this seems computationally difficult and therefore does not fit to complex circuits. Other techniques proposed in [28][29][30]36] rely on the notion of capturing the delay distribution by performing the statistical static timing analysis instead of static timing analysis. Later, gate sizing is carried out using either nonlinear prog...

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“…Even though the reduction of leakage in the multi gate finFET technology in comparison with the bulk MOSFET, the focus remains on the same areas of the design [3] and predicting the speed and the energy of a design is an overriding concern. While Spice simulations remain the reference technique in estimating delay and energy consumption at logic level due its very high accuracy, it also takes a very long time for computation [10].…”

Section: Introductionmentioning

confidence: 99%

Novel methodology to determine leakage power in standard cell library design

Charafeddine¹,

Ouardi²

2020

Heliyon

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In the most advanced technology nodes, leakage has become a major concern for integrated circuits designers. In addition, the leakage calculation using SPICE simulations takes a large amount of time for the entire library of standard cells for the different PVT (Process, Voltage, and Temperature) conditions. However IC Designers usually need a fast access to the leakage current estimation in order to validate their designs. In this context, the present paper proposes a new approach of the leakage estimation. The aim of this methodology is to predict the leakage of a standard cell accurately and in a short amount of time. This method is applied to all the cells of the used standard cell library and is based on mathematical models developed from the leakage physical equation. The results of the leakage calculated with this technique shows an average error of 5%. The context of this work is part of a fast generation of a full liberty file of a standard cell library using the curve fitting method.

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A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

Cited by 28 publications

References 26 publications

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

Novel methodology to determine leakage power in standard cell library design

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