A VLSI chip for wavelet image compression

Schwarzenberg, Markus; Traber, Markus; Scholles, M.; Schüffny, René

doi:10.1109/iscas.1999.779994

Cited by 4 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to show the versatility of the proposed Gaussian function generator, the I G current generator circuit was disabled in the results presented in Figs. 9-11; these results correspond to the realization of equation (9). The bias conditions for the transistors were, I G =750 nA, I B =500 nA and I σ = 2.5 µA.…”

Section: Resultssupporting

confidence: 61%

“…Recently, wavelet transforms have been implemented using digital circuit techniques [5][6][7][8][9][10]; however, the practical impact of these realizations in battery-operated systems has been limited mainly because they require large amounts of silicon area. Also, the implementation of the Continuous Wavelet Transform (CWT) has been reported in the literature [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient circuit implementation of morlet wavelets

Meléndez-Rodríguez

Silva-Martínez

Spencer³

2005

JART

View full text Add to dashboard Cite

A family of versatile building blocks intended for the implementation of Morlet wavelets is proposed. The circuits are compact, fully programmable, and well suited for low-voltage and low-power applications. The resulting wavelet is temperature compensated and low sensitive to process parameter variations. Using current sources can independently control the main wavelet parameters. Hspice and breadboard results demonstrate the feasibility of both the wavelet realization and proposed circuits.

show abstract

Section: Resultssupporting

confidence: 61%

Section: Introductionmentioning

confidence: 99%

Efficient circuit implementation of morlet wavelets

Meléndez-Rodríguez

Silva-Martínez

Spencer³

2005

JART

View full text Add to dashboard Cite

show abstract

“…In [69], a VLSI circuit for wavelet image compression was reported. In the proposed architecture, there are four major processing elements: (i) a data format conversion processing element, which converts the raw pixel value from BAYER-RGB format into BAYER-YYC r C b format; (ii) a wavelet transformunit, which performs 1-D wavelet transforms firstly on rows and then on columns; (iii) a binary adaptive quantizer, which quantizes the wavelet transform coefficients; (iv) a significant coefficient pyramid coder, which further reduces the coding redundancy.…”

Section: High-performance Compression-processor Designmentioning

confidence: 99%

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

Zhang

Bermak

2010

Journal of Sensors

View full text Add to dashboard Cite

Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

show abstract

“…The developments of binary and morphological image processing algorithms were accelerated. These algorithms include noise reduction [3], image sharpening [4], edge detection [2], image compression [5] and many other morphological filters. Large numbers of image processing software packages and hardware peripherals now include morphological operation such as dilation and erosion.…”

Section: Previous Workmentioning

confidence: 99%

<title>On-chip binary image processing with CMOS image sensors</title>

Hong¹,

Hornsey

2002

SPIE Proceedings

View full text Add to dashboard Cite

In this paper, we demonstrate a CMOS active pixel sensor chip, integrated with binary image processing on a single monolithic chip. A prototype chip comprising a 64x64 photodiode array with on-chip binary image processing is fabricated in standard 0.35 µm CMOS technology, with 3.3V power supply. The binary image processing functionality is embedded in the column structure, where each processing element is placed per column, reducing processing time and power consumption. This column processing structure is scalable to higher resolution. A 3x3 local mask (also called structure element) is implemented every column so that row-parallel processing can be achieved with a conventional progressive scanning method.

show abstract

A VLSI chip for wavelet image compression

Cited by 4 publications

References 3 publications

Efficient circuit implementation of morlet wavelets

Efficient circuit implementation of morlet wavelets

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

<title>On-chip binary image processing with CMOS image sensors</title>

Contact Info

Product

Resources

About