A VLSI architecture for a half-edge-based corner detector

Ranganathan, N.; Nichani, S.; Mehrotra, R.

doi:10.1007/bf01230199

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…Bhanu et al have designed and implemented a real-time segmentation processor which makes use of a gradient relaxation algorithm (iterative) to assign pixels into classes, based on their gray value and the gray values of neighboring pixels [11]. Ranganathan et al have proposed a VLSI architecture which convolves images with eight 15x15 kernels in order to implement a technique for corner detection which is based on the concept of half-edge and on the first derivative of Gaussian [12]. Cheng et al utilized the theory of dynamic programming to develop a backtracking method for curve detection and designed an associated VLSI architecture which solves the problem in O(n) time, where n is the length of the curve to be found [13].…”

Section: Introductionmentioning

confidence: 99%

VLSI Implementation of Contour Extraction from Real Time Image Sequences

Melcher¹,

Naviner²,

Carvalho³

et al. 1997

VLSI: Integrated Systems on Silicon

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In this work a parallel architecture is proposed for VLSI implementation of a dataflow algorithm for 20 boundary (or contour) detection. The algorithm works on the gradient image and uses a set of primitive paths to generate all possible contour paths on a neighborhood defined by a 5x5 window. The objective is to determine whether or not the neighborhood central pixel belongs to a continuous boundary line passing across the window. Test results show that one-pixel wide continuous boundary lines can be extracted using this algorithm.

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Section: Introductionmentioning

confidence: 99%

VLSI Implementation of Contour Extraction from Real Time Image Sequences

Melcher¹,

Naviner²,

Carvalho³

et al. 1997

VLSI: Integrated Systems on Silicon

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Image analysis and computer vision: 1991

Rosenfeld¹

1992

CVGIP: Image Understanding

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A Two-dimensional Systolic Array Processor for Image Processing

Ranganathan

Patell²,

McCabe³

The Fifth International Conference on VLSI Design

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processing and since-an 8-bit multiplier -is expensive in terms of silicon area, most previously proposed twodimensional arrays use a single-bit processing element. levels bit processor, but can yield significant improvements in The performance of sequential computers in the rapidly expanding fields of image processing and vision has been found to be quite inadequate since most From our analysis, we have found that a 4-bit processing applicationsProcessing Of the image frame(s) in element requires a slightly kgFer silicon area than a time' A ' 12 512 image frame with 256 requires roughly 256K pixels of 8 bits each for storage performanm. and most applications today, e.g. optical flow and motion This paper reports on our on-going research towards analysis, require the storage and processing of mutliple vLsl processor architecture for ima,ge processing applications.processing, the obvious solution is to design parallel The processor architecture is based on a sIMD array of 4-algorithms and architectures that can be bit processing elements, interconnected by a mesh image network with four nearest neighbors. Each processing processing and vision techniques are based on spatial frames at high speeds' with the rapid gowth in design and ~p l e m e n~t i o n , of a two-dimensional array and the advances made in vLsl and wsl Many 0-8186-2465-5IQ1 $1.00 0 1991 IEEE 215

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A VLSI architecture for a half-edge-based corner detector

Cited by 4 publications

References 9 publications

VLSI Implementation of Contour Extraction from Real Time Image Sequences

VLSI Implementation of Contour Extraction from Real Time Image Sequences

Image analysis and computer vision: 1991

A Two-dimensional Systolic Array Processor for Image Processing

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