A VLSI approach to the implementation of additive and shunting neural networks

Pelayo, Francisco J.; Vidal, Eduardo Ros; Martín-Smith, P.; Fernandez, Francisco Javier Ramírez; Prieto, Alberto

doi:10.1007/3-540-59497-3_244

Cited by 5 publications

(2 citation statements)

References 12 publications

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“…The CMOS circuit implementation of a single positive term or excitatory synapse is shown in Fig. 8 [19]. A dual version of this circuit implements an inhibitory one.…”

Section: Cmos Circuits For Multiple Chip Cnns Using Spikesmentioning

confidence: 99%

“…For each input pulse, the capacitor C + i is suddenly discharged and then a current is injected on the output node during the time required to charge C + i up to either V x (shunting terms) or to the reference voltage V r,i (linear terms). For a given input spike frequency F + i , the contribution of the synapse to the "membrane potential V x " can be approximated by [19]:…”

Section: Cmos Circuits For Multiple Chip Cnns Using Spikesmentioning

confidence: 99%

See 1 more Smart Citation

Focal-Plane and Multiple Chip VLSI Approaches to CNNs

Anguita

Pelayo

Ros

et al. 1998

Cellular Neural Networks and Analog VLSI

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Abstract. In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photosensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane image processing applications. The third one allows, since its dynamics is defined by process-independent local ratios and its input/outputs can be efficiently multiplexed in time, the construction of very large multiple chip CNNs for more complex vision tasks.

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“…The CMOS circuit implementation of a single positive term or excitatory synapse is shown in Fig. 8 [19]. A dual version of this circuit implements an inhibitory one.…”

Section: Cmos Circuits For Multiple Chip Cnns Using Spikesmentioning

confidence: 99%

Section: Cmos Circuits For Multiple Chip Cnns Using Spikesmentioning

confidence: 99%