A virtual hardware handler for RTR systems

Turner, Ray W.; Woods, Roger; Sezer, Sakir; Heron, J.

doi:10.1109/fpga.1999.803689

Cited by 2 publications

(1 citation statement)

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“…Therefore, configuration compression can be utilized to achieve less reconfiguration overhead in run-time reconfigurable systems. Many different algorithms have been proposed in literature to perform compression on configuration data [65,66]. Some of these algorithms use general coding methods like run-length coding to compress the configurations [67] while some of them achieve compression by reuse of the data for configuring several programmable elements.…”

Section: Minimizing the Configuration Datamentioning

confidence: 99%

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Shoa

Shirani

2005

J VLSI Sign Process Syst Sign Image Video Technol

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Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.

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Section: Minimizing the Configuration Datamentioning

confidence: 99%