A Virtual Fault Injection Framework for Reliability-Aware Software Development

Höller, Andrea; Macher, Georg; Rauter, Tobias; Iber, Johannes; Kreiner, Christian

doi:10.1109/dsn-w.2015.16

Cited by 20 publications

(5 citation statements)

References 10 publications

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“…In using the tools, if there is no need for a specific need for functionality, using the original tools is recommended as there are additional overheads incurred by the modified tools. For instance, [63] is an extension of [54] with additional overhead and support for advanced memory and processor fault models. Similarly, [61] is an add-on functionality on [44] with an additional overhead of about 10X of normal QEMU environment and JIT fault injection added functionality.…”

Section: Evaluation Methodologymentioning

confidence: 99%

“…In [63] a virtual FI framework that simulates safetystandard aligned fault models and supports COTS software implementations, as well as popular edge device embedded processors is presented. The work also shows the procedure for integrating the framework into various software development stages.…”

Section: D-cloud/faultvmmentioning

confidence: 99%

“…• Memory -The memory cells such as RAM and related parts are tested [44], [45], [46], [47], [50], [51], [54], [55], [63]. • Registers -General purpose and special purpose registers are tested in [44], [45], [48], [49], [50], [51], [53], [54], [58], and [66].…”

Section: A Components Tested For Reliabilitymentioning

confidence: 99%

“…• Transient [39], [48], [49], [53], [58], [63] • Intermittent [48], [58], [63] • Permanent [45], [48], [49], [50], [54], [58], [63], [66] faults. There are faults such as packet drop and packet modification [55], memory-state-aware faults [47], and faulty instructions [44] used by different tools.…”

Section: B Fault Modeling Approachmentioning

confidence: 99%

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A Survey of QEMU-Based Fault Injection Tools & Techniques for Emulating Physical Faults

2023

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Fault Injection (FI) is a method used to quantify the reliability and resilience of a system by assessing the system's ability to detect, locate, and/or mitigate fault occurrences. At the architecture level, targeted bit flips at specific times and locations can help quantify the response of a running application to unwanted changes in state and memory values. FI campaigns of this type can be performed on the target hardware virtual implementations of the target device. In this paper, we present a survey of Quick EMUlator (QEMU) based FI techniques. After discussing the various techniques proposed by academia and industry, we classified them into categories and compare their attributes. This review will help researchers understand the capabilities and limitations of using the QEMU emulator for FI-based system reliability analysis. Additionally, we identify the gaps in existing techniques and propose opportunities for extensions.

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Section: Evaluation Methodologymentioning

confidence: 99%

Section: D-cloud/faultvmmentioning

confidence: 99%

Section: A Components Tested For Reliabilitymentioning

confidence: 99%

Section: B Fault Modeling Approachmentioning

confidence: 99%

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A Survey of QEMU-Based Fault Injection Tools & Techniques for Emulating Physical Faults

2023

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“…An ISS usually only simulates the architectural registers, but not any micro-architectural registers. ISSs are used for fault injection in [14,24,35]. In software-level fault injection, the fault is directly injected into a variable of the executing program.…”

Section: Simulation-based Fault Injectionmentioning

confidence: 99%

Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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