A View on Annealing Behavior of Cu-Filled Through-Silicon Vias (TSV)

Huang, Lingang; Deng, Qiong; Li, Ming; Feng, Xue; Gao, Liming

doi:10.1149/2.0091607jss

Cited by 9 publications

(3 citation statements)

References 29 publications

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“…On the other hand, the structure around TSV can be pulled by protrusion of TSV-Cu, which will cause the metal interconnect layer to break (e.g. BEOL layer) [24].…”

Section: Protrusionmentioning

confidence: 99%

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Yuan¹,

Zhang²,

Xia³

et al. 2019

IJPE

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TSV technology can achieve heterogeneous integration by stacking different technologies and functions of logic chip, memory, MEMS, etc., as a system. There are many significant advantages for heterogeneous integration in terms of cost, performance, and time to market. TSV technology has the potential to improve 3D packaging. As the important physical connection and electrical connection between the chips, TSV's reliability is undoubtedly the key to determine the reliability of TSV three-dimensional integrated devices. As a new interconnect technology, TSV technology faces many process difficulties and challenges. Its reliability has not been fully studied and guaranteed. The process optimization and reliability improvement of TSV have become a hot topic in recent years. Recognition process defects and analysis of the failure mechanism play important roles in the optimization and improvement of design, production, and use of TSV three-dimensional integrated devices. In this paper, the square TSV and circular TSV with different ratios were researched by microphysical analysis and data analysis. The analysis results revealed the key technological factors and physical mechanism of formation of the TSV defects, which can support TSV device development, production, and reliable application.

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“…On the other hand, the structure around TSV can be pulled by protrusion of TSV-Cu, which will cause the metal interconnect layer to break (e.g. BEOL layer) [24].…”

Section: Protrusionmentioning

confidence: 99%

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Yuan¹,

Zhang²,

Xia³

et al. 2019

IJPE

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“…1,2 The micro vias are generally filled by the electrodeposition of copper (Cu). 3,4 Defects usually appear in the filled micro vias, as the gradient distribution of the electrolyte mass is inevitably formed from the opening to the bottom of the micro vias. 5 In order to avoid such defects, multiple additives are generally needed for the micro via filling process.…”

mentioning

confidence: 99%

Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

Wang

et al. 2020

J. Electrochem. Soc.

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In this study, by adding a single additive of Cetyltrimethyl Ammonium Bromide (CTAB) to the electrolyte, the bottom-up filling of micro via (Φ20 μm × 200 μm) was obtained with a fast filling rate. Accordingly, it was found that CTAB has a better diffusion performance and electrodeposition inhibition effect compared to a typical suppressor and leveler. Moreover, the filling results of the micro vias indicated that CTAB can be transported to the deep region of the micro via, successfully limiting the growth of Cu on the sidewall in these regions.

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“…Compared with two-dimensional packaging, the short interconnections in 3D packaging effectively improve the electrical properties, including transition speed, bandwidth, and power consumption. [4][5][6][7] TSVs allow one to realize high-density 3D packaging, which has attracted considerable research interest in extending Moore's law. Normally, the fabrication of TSVs includes etching, insulation layer deposition, barrier layer deposition, copper filling, and wafer thinning.…”

mentioning

confidence: 99%

Electroless Grafting of Polymer Insulation Layers in Through-Silicon Vias

Liu

Han

Zhang

et al. 2019

ECS J. Solid State Sci. Technol.

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A through-silicon via (TSV) with a polymeric insulation layer is promising in three-dimensional packaging technology because of its outstanding electrical properties. In this study, we present an electroless grafting method to realize the fabrication of a thin insulation layer in high aspect ratio TSVs. The proposed method is based on the polymerization of a vinyl monomer and an aryl diazonium salt on a silicon surface. Both poly(acrylic acid) and poly(methyl methacrylate) insulation layers were successfully prepared in TSVs to demonstrate the feasibility of the proposed method to fabricate hydrophilic and hydrophobic layers. The resulting polymer insulation layer exhibited high step coverage and superior dielectric properties. The electroless grafting method is a novel synthesis route to prepare polymeric insulation layers with outstanding dielectric properties in high aspect ratio TSVs.

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A View on Annealing Behavior of Cu-Filled Through-Silicon Vias (TSV)

Cited by 9 publications

References 29 publications

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

Electroless Grafting of Polymer Insulation Layers in Through-Silicon Vias

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