A video decoder for H.261 video teleconferencing and MPEG stored interactive video applications

Brinthaupt, D.; Letham, L.; Maheshwari, Vikas; Othmer, J.; Spiwak, R.; Edwards, B.; Terman, C.J.; Weste, N.

doi:10.1109/isscc.1993.280095

Cited by 27 publications

(3 citation statements)

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“…There are also many MPEG application-specific integrated circuit (ASIC) chips that contain a RISC core for control and housekeeping purposes. The most successful approach right now belongs to these classes [14]- [16], but in this paper, such chips are omitted for proceeding processor architectural considerations.…”

Section: A Historymentioning

confidence: 99%

Multimedia processors

Kuroda

Nishitani

1998

Proc. IEEE

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This paper describes recent large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. Recent general-purpose microprocessors for workstations and personal computers (PC's) use special built-in hardware for multimedia processing, so the multimedia processors described in this paper include these modified general-purpose microprocessors. After briefly reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PC's, embedded RISC's, low-power digital signal processors (DSP's), which are mainly used for mobile communications devices, and media processors that support PC's for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSP's. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including "system on a chip," and their applications are also discussed.

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Section: A Historymentioning

confidence: 99%

Multimedia processors

Kuroda

Nishitani

1998

Proc. IEEE

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“…The video-decoder chip (AVP-4220D) 6 is designed to decode full-motion video, according to the Px64 and MPEG standards. The decoderaccepts compressed-video data at rates up to 4 Mb/s from either the serial bus or the parallel host bus viathe host!serialinterface.…”

Section: Decodermentioning

confidence: 99%

A Video-Codec Chip Set for Multimedia Applications

Ackland

Aghevli

Eldumiati

et al. 1993

At&T Technical Journal

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The multimedia, video‐codec chip set described in this paper represents the first generation in a family of devices that will make possible reliable, cost‐effective storage and transmission of multimedia data, including video. AT&T's multimedia video‐codec complies with international video standards. It supports still‐image and audio compression over a wide range of quality and bit rates; multiplexing of audio, video, and data; and protocol control for a variety of telecommunications options. The codec consists of three chips—a video encoder, a video decoder, and a systems controller—plus one or two digital‐signal processors and a modest amount of industry‐standard, dynamic random‐access memory. In this paper, we examine the potential market for such a device and the performance and capability requirements. We also describe the overall multimedia‐codec architecture and review the video‐signal‐processing operations for standards‐compliant video compression. Finally, we describe the architecture of the encoder, decoder, and systems controller.

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“…As a result, motion compensation with half-pel accuracy is recommended in MPEG standards [29], [30]. Implementations of half-pel motion estimation have started to be realized [3], [6], [40].…”

Section: Introductionmentioning

confidence: 99%

Interpolation-free subpixel motion estimation techniques in DCT domain

Koc¹,

Liu

1998

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Currently existing subpixel motion estimation algorithms require interpolation of interpixel values which undesirably increases the overall complexity and data flow and deteriorates estimation accuracy. In this paper, we develop discrete cosine transform (DCT)-based techniques to estimate subpel motion at different desired subpel levels of accuracy in the DCT domain without interpolation. We show that subpixel motion information is preserved in the DCT of a shifted signal under some condition in the form of pseudophases, and we establish subpel sinusoidal orthogonal principles to extract this information. The proposed subpixel techniques are flexible and scalable in terms of estimation accuracy with very low computational complexity O(N 2 ) compared to O(N 4 ) for the full-search block-matching approach and its subpixel versions. Above all, motion estimation in the DCT domain instead of the spatial domain simplifies the conventional hybrid DCT-based video coder, especially the heavily loaded feedback loop in the conventional design, resulting in a fully DCT-based high-throughput video codec. In addition, the computation of pseudophases is local, and thus a highly parallel architecture is feasible for the DCT-based algorithms. Finally, simulation on video sequences of different characteristics shows comparable performance of the proposed algorithms to block-matching approaches.

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A video decoder for H.261 video teleconferencing and MPEG stored interactive video applications

Cited by 27 publications

References 1 publication

Multimedia processors

Multimedia processors

A Video-Codec Chip Set for Multimedia Applications

Interpolation-free subpixel motion estimation techniques in DCT domain

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