A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig

Vallet, Mathieu; Richard, Olivier; Deval, Yann; Belot, Didier

doi:10.1109/s3s.2014.7028234

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“…As a crucial component of the fractional-N frequency synthesizer, the frequency divider puts forward higher requirements. Therefore, a high operating speed and low power consumption fractional-N frequency divider are highly desired [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The working speed limitation of pulse swallow frequency divider is determined by the delay time of MC signal (τ MC ) [1,2,3,20,21,22,23,24,25,26].…”

Section: Introductionmentioning

confidence: 99%

A modified pulse swallow frequency divider for fractional-N PLL

Yan

Jiang

Liu

et al. 2020

IEICE Electron. Express

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A modified pulse swallow frequency divider for fractional-N frequency synthesizers was designed and implemented in a 0.18 µm CMOS process. The proposed structure inserts a pulser between D flip-flop 1 (DFF1) and B counter to solve the possible malfunction of the SR latch and the unwanted division ratio offset in the conventional structure. To remarkably improve the operating speed, a D flip-flop 2 (DFF2) was employed to retime the modulus control (MC) signal. The proposed frequency divider can work at an input clock signal frequency up to 7.04 GHz with a power consumption of only 7.59 mW.

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