A vertical resonant tunneling transistor for application in digital logic circuits

Stock, J.; Malindretos, J.; Indlekofer, K. M.; Pottgens, M.; Förster, A.; Lüth, H.

doi:10.1109/16.925221

Cited by 51 publications

(18 citation statements)

References 12 publications

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“…This gives rise to a characterisitic peaked I-V characteristic ( Fig. 2b) with negative differential resistance (NDR): The strongly non-linear I-V characteristics allows applications of RTDs for high frequency generation (up to 700 GHz realized) and for low complexity, multi-valued logic circuits [10]. A major figure of merit of such RTD devices is the so-called peak-to-valley ratio (PVR) of its I-V characteristic.…”

Section: Interface Roughness and Quantum Devicesmentioning

confidence: 99%

Research on III-V Semiconductor Interfaces: Its Impact on Technology and Devices

Lüth

2001

phys. stat. sol. (a)

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The paper presents some examples of interface studies which are intimately related to progress in III-V semiconductor technology and device physics. Optical in-situ investigations of the MOVPE growth of InGaP/InP layers are essential for the control of ordering phenomena in these layers which are relevant for high performance optoelectronic devices. Interface roughness, which is an essential parameter for the performance of heterostructure quantum devices, is a typical topic of interface investigations by e.g. transmission electron microscopy or X-ray scattering. As a further example studies on electronic interface states on metal/narrow gap III-V semiconductors are presented which enabled the successful preparation of semiconductor/superconductor hybrid devices. For group III-nitrides with wurtzite structure the interplay of internal polarisation fields and charges in surface states yields new challenges in order to understand and control Schottky barrier heights and 2D confinement in heterostructure FETs.

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Section: Interface Roughness and Quantum Devicesmentioning

confidence: 99%

Research on III-V Semiconductor Interfaces: Its Impact on Technology and Devices

Lüth

2001

phys. stat. sol. (a)

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“…In order to control the resonant current effectively, the self-aligned gate metal is made near the vertical side of emitter mesa to narrow the current channel cross section area, which is left by depletion region produced by the reverse gate voltage. The function of the two gate structures can be described as follows [3]:…”

Section: Materials Structure Designmentioning

confidence: 99%

“…It falls into two kinds: one is gate RTT, whose I-V characteristics can be controlled by the third terminal -gate terminal based on the RTD structure [2,3] and the other is compound RTT, whose DBS structure is combined with another high frequency three terminals device, such as HEMT [4], MESFET [5], HBT [6].…”

Section: Introductionmentioning

confidence: 99%

The design and fabrication on gate type resonant tunneling transistor

Guo

Liang

Song

et al. 2008

Front. Electr. Electron. Eng. Ch

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In light of fabricating resonant tunneling diode (RTD), in this paper a GaAs-based resonant tunneling transistor with gate structure (GRTT) has been designed and fabricated successfully. A systematic depiction centers on the designs of material structure, device structure, photolithography mask, fabrication of device and the measurement and analysis of parameters. The fabricated GRTT has a maximum PVCR of 46 and a maximum transconductance of 8 mS. The work lays the foundation for further improvement on the performance and parameters of RTT.

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“…Previous proposals for tunnel diode logic have been based on the merging of two terminal devices with FETs of various forms (e.g. [5], [48]), although a static latch circuit may be as simple as two series-connected RTDs [44]. Figure 6 shows the output of a SPICE simulation of the CNT within its quantum confinement region illustrating the negative differential resistance (NDR) characteristic of RTDs.…”

Section: Carbon Nanotube Devicesmentioning

confidence: 99%

Exploiting multiple functionality for nano-scale reconfigurable systems

Beckett¹

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a result, these systems may come to be characterised by vast arrays of largely identical devices that are differentiated via postfabrication configuration -but only if low-overhead configuration can be achieved. Two simulation studies are presented that describe some ideas for achieving low-overhead reconfigurability in systems built from nano-scale components. The first is based on variable-threshold devices built from thin-body double gate transistors while a second, more speculative idea is based on recently identified resonant tunneling behaviour in carbon nanotubes. Various logic functions can be configured via the application of a simple bias voltage. Further, two approaches to the issue of generating the required bias voltages based on RTD devices and chalcogenide films are briefly explored.

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A vertical resonant tunneling transistor for application in digital logic circuits

Cited by 51 publications

References 12 publications

Research on III-V Semiconductor Interfaces: Its Impact on Technology and Devices

Research on III-V Semiconductor Interfaces: Its Impact on Technology and Devices

The design and fabrication on gate type resonant tunneling transistor

Exploiting multiple functionality for nano-scale reconfigurable systems

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