A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology

Lue, Hang-Ting; Hsu, Tzu-Hsuan; Yeh, Teng-Hao; Chen, Wei‐Chen; Lo, Chieh Roger; Huang, Chien‐Chang; Lee, Guan-Ru; Chiu, Chia-Jung; Wang, Keh-Chung; Lu, Chih‐Yuan

doi:10.1109/vlsitechnology18217.2020.9265037

Cited by 11 publications

(5 citation statements)

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“…Diminishing power dissipation of flash memories is quite crucial in energy constrained environment, such as potable equipment, smart cards, and Internet of Things (IoT). [4][5][6][7][8] Nevertheless, the current load in output end of charge pump dominating the total power dissipation of memory system mainly comprises the short current of LS, which makes energy saving of LS essential.…”

Section: Introductionmentioning

confidence: 99%

“…With regard to the conversion of these voltage regions, LS (level shifter) can convert the logic signals of peripheral circuits into high voltage levels, providing the interaction between these circuits working at different voltage ranges. Diminishing power dissipation of flash memories is quite crucial in energy constrained environment, such as potable equipment, smart cards, and Internet of Things (IoT) 4–8 . Nevertheless, the current load in output end of charge pump dominating the total power dissipation of memory system mainly comprises the short current of LS, which makes energy saving of LS essential.…”

Section: Introductionmentioning

confidence: 99%

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An energy‐efficient level shifter based on a differential cascade voltage switch structure

Zhang

Liu

et al. 2022

Circuit Theory & Apps

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Based on differential cascade voltage switch architecture, this paper proposes a level shifter with optimized energy consumption, constructed by stacking diode‐connected NMOS and PMOS transistors and splitting input signals of the two output stages. Eventually, the overlap time of input signals of the two output stages has been reduced, during which there is a considerable short‐current from high voltage source to ground. When implemented in a 110 nm CMOS process, post‐layout netlist simulations show that the proposed level shifter exhibits a 2.31 ns switching delay and 819 fJ energy consumption when converting a 1.5 V input signal into 4.5 V with 10 MHz operational frequency and 15 fF output load.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An energy‐efficient level shifter based on a differential cascade voltage switch structure

Zhang

Liu

et al. 2022

Circuit Theory & Apps

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“…Meanwhile, vertical NWFET is one of the promising candidates which can have device design flexibility by large CPP margin since the channel is aligned vertically [8]- [11]. In addition, vertical NWFETs along with BPR possibly ease 3D MOL layout schemes by forming power delivery lines at the bottom.…”

Section: Introductionmentioning

confidence: 99%

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

et al. 2021

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Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay (CggVdd/Ion, where Cgg is gate capacitance, Vdd is operation voltage, and Ion is on-state current) at the fixed off-state currents, and analog performance is quantified by the product of cutoff frequency (Ft) and transconductance efficiency (Gm/Ids). ML accurately predicted the geometry and doping parameters suggesting the best device performances. All the optimized NWFETs have larger drain diameters but smaller source diameters at the minimum of gate lengths, gate oxide thicknesses, drain junction gradients, and source/drain spacer lengths. Small source diameters are needed to tightly control the energy barrier to reduce the short-channel effects, whereas large drain diameters increase current drivability than Cgg. Small drain junction gradients increase the lateral electric field from source to drain, which increases the carrier velocity. Longer spacer lengths decrease both Ion and Cgg, but the Ion degradation is critical. These device characteristics validate the optimization results from ML, and ML-based optimization is fast and effective to maximize both digital and analog performances.

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“…and dataintensive treatment, exacerbates the requirement in terms of performances and memory capacity on edge devices, such as the high-end Micro Controller Unit (MCU). In this context, highdensity memory based on emerging concept could replace actual solutions such as 1.5T NOR Flash memory or 1T1R Phase Change Memory (PCM) [1][2][3][4][5][6][7]. In this context, to decrease drastically the bit cell footprint, a back-end selector solution could be adopted.…”

Section: Introductionmentioning

confidence: 99%

A Self-referenced and regulated sensing solution for PCM with OTS selector

Gasquez

Giraud

Boivin

et al. 2021

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)

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Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and the sneak-path management. To tackle this challenge, we propose in this paper, a new sense amplifier able to generate an autoreference taking into account leakage current of unselected cell, including a regulation loop to compensate voltage drop due to reading current sensing. This auto-referenced sense, built on the charge-sharing principle, is designed on a 28nm FDSOI technology and validated through extensive Monte-Carlo and corner cases simulations. From the simulation results, our sense amplifier is demonstrated to be robust for an ultra-large range of sneak-path current and consequently for a large range of memory array size, suitable for embedded memory in high-end microcontroller.

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A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology

Cited by 11 publications

References 0 publications

An energy‐efficient level shifter based on a differential cascade voltage switch structure

An energy‐efficient level shifter based on a differential cascade voltage switch structure

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

A Self-referenced and regulated sensing solution for PCM with OTS selector

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