A versatile high speed bit error rate testing scheme

Fan, Yongquan; Zeljko, Z.; Chiang, Man Wah

doi:10.1109/isqed.2004.1283706

Cited by 9 publications

(1 citation statement)

References 8 publications

(7 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In hardware test engineering circles, stimuli generators are commonly known as automatic test pattern generators (ATPGs). Also, hardware-based performance checkers such as the BERT [12] are also common in hardware tester systems. Figure 2 shows the proposed transaction-based hardware architecture for SoC/NoC designs.…”

Section: Overview Of Bus Interconnects Transaction-level Modelingmentioning

confidence: 99%

Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

Kho¹,

Munusamy

2014

2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolo

View full text Add to dashboard Cite

Transaction-level Modeling (TLM) and bus functional modeling (BFM) are widely-used techniques for functional verification of digital systems. Many modern systems-on-chip (SoC), network-on-chip (NoC), application-specific integrated circuit (ASIC), and field-programmable gate array (FPGA) designs have been verified using these techniques. However, transactionbased techniques have almost always [1]-[14] been used only for simulation of digital designs, and until recently, were not used to design physical hardware.This paper introduces a technique to develop transactionbased hardware. With this method, the same transaction-based model can both be simulated and synthesized to hardware. Several SoC/NoC subsystems can easily be interconnected in basically the same manner as how transaction-based simulation models are being written. This approach brings the benefits of transaction-based verification (TBV) to the hardware design engineers, resulting in a greater level of simplification for complex designs.

show abstract

Section: Overview Of Bus Interconnects Transaction-level Modelingmentioning

confidence: 99%

Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

Kho¹,

Munusamy

2014

2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolo

View full text Add to dashboard Cite

show abstract

A Versatile FPGA-Based Multi-Rate and Multi-Channel Transmission Loss Tester

Gong

et al. 2018

2018 24th Asia-Pacific Conference on Communications (APCC)

View full text Add to dashboard Cite

Bit error rate testing scheme for digital communication devices

Marda

Vaishnav

Rao

2014

Proceedings of the 2014 International Conference on Control, Instrumentation, Energy and Communication (CIEC)

View full text Add to dashboard Cite

In the present era, digital transmission of data plays a vital role in every sector. The main aim of this paper is to design a cost effective device which can test a transmission data and find the errors if any at the receiving end. Products based on this concept, having customizable options are widely available but with high cost. Most of the options in the testing equipment are unused, so there has been a requirement of a customized IP based tester with V.35 and PCM E1 framer which can serve in testing MODEMS. The 32 bit microcontroller STM32 monitors all the blocks on the testing board. The peripherals are connected to STM32 using various interfaces. The pattern generated is modulated on the transmission side of E1 framer or V.35. The MODEM receives the pattern and loops back it to the receiver section of E1 framer or V.35. Here the pattern is recovered via demodulator and passed to the BERT (Bit Error Rate Tester). If both are same then there will be no Bit Error, otherwise status register and bit error register values get updated automatically indicating the possibility of the error. The number of patterns generated by BERT is 23 and can be connected with multiple modems to test their working corresponding to different patterns. This process ensures the communication between MODEMS and BERT in a safest mode. Keywords-Bit Error Rate, Microcontroller, E1 Framer, BERT, Modem.

show abstract

A versatile high speed bit error rate testing scheme

Abstract: Abstract

Cited by 9 publications

References 8 publications

Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

A Versatile FPGA-Based Multi-Rate and Multi-Channel Transmission Loss Tester

Bit error rate testing scheme for digital communication devices

Contact Info

Product

Resources

About