A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

Abstract

This paper presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitivecoupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 µm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of dVSSF/dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM 1 and FoM 2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

CMOS design of a capacitively isolated AC switch driver for auto-turning frequency

“…To deal with a floating ground design, capacitive isolations [11][12][13][14] and capacitive-coupled level shifters [15][16][17] are two major approaches found in the literature. However, as mentioned above, the floating ground within an AC-switch is an alternative analog signal.…”

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

“…Existing high-voltage level shifters have employed a number of design techniques to improve dV/dt immunity [13][14][15]. In [13], the author proposed a level shifter based on high-bandwidth current and latch structure; the delay is 370 ps, but the dV/dt slew immunity is only 30 V/ns.…”

“…Yang et al adopted a new technique to enhance the slew rate of level shifters, achieving a novel level shifter with 120 V/ns immunity and 20 ns propagation delay [14]. The level shifter (LS) proposed in [15] is designed with a current mirror/latch structure, and a common-mode noise canceller is also applied to enhance the dV/dt immunity. This level shifter achieves 200 V/ns noise immunity and sub-nanosecond delay in the SOI process, but this good performance is limited by the process.…”

“…As a result, several conventional structures designed to enhance the dV/dt noise immunity of the level shifters become inappropriate as the power supply voltage rises. Existing high-voltage level shifters have employed a number of design techniques to improve dV/dt immunity [13][14][15]. In [13], the author proposed a level shifter based on high-bandwidth current and latch structure; the delay is 370 ps, but the dV/dt slew immunity is only 30 V/ns.…”

A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver

“…Compared to inductive isolation, capacitive isolation operates on electric fields alone and can be used without interference from the magnetic field of the surrounding MRI equipment. Additionally, the robustness under fast transient changes makes it more advantageous [11]. Due to the higher data rate, lower latency, and reduced cost, the capacitive isolator has gradually replaced the traditional magnetic coupler isolator in many applications.…”