A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing

Kumar, Vivek; Selvaraj, Ratnam J.; Nithya, D.; Kousik, N.V.

doi:10.1016/j.micpro.2019.102875

Cited by 17 publications

(8 citation statements)

References 11 publications

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“…Table 10 compares the performance of the proposed DCAM with various state of art multipliers like FDM [26], MBIM [28], EEPAL [29], and CVMP [27]. From the 13 Journal of Nanomaterials simulations, it is observed that the proposed DCAM resulted in superior performance, because it utilizes the delay controller environment for data transfer from one module to another module.…”

Section: Resultsmentioning

confidence: 99%

“…The carry propagate adders are designed with a 4 : 2 compressor to reduce the height of the partial product rows. Further, CNTFET-based vedic mathematics processor (CVMP) [27] is developed to reduce the power complexities presented in the FDM, which performs additions, multipliers, multiply and accumulations, and DWT operations. The maximum height of the partial product was reduced by one unit.…”

Section: Related Workmentioning

confidence: 99%

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Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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“…5.12 Biomedical signal processing (FinFET & CNTFET technology) [29] Describe a new approach for VM-based DWT implementation in biomedical signal processing. The use of alternate devices in a low-power architecture scheme is a silent element of the work.…”

Section: Identifying Breast Cancer Automatically Using Vmmentioning

confidence: 99%

“…Also design of processor core of the system on chip is based on Vedic Maths sutras (SoC). This paper [29] combines the competence of Vedic Maths with improvements in low-power VLSI. The CNTFET concept diminishes power by around 95% while also controlling voltage.…”

Section: Identifying Breast Cancer Automatically Using Vmmentioning

confidence: 99%

Applications of Vedic multiplier - A Review

Khubnani¹,

Sharma²,

Subramanyam³

2022

J. Phys.: Conf. Ser.

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Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.

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“…In recent years, different researchers have done several works [2][3][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Reference [22] proposes a high throughput MAC architecture that promises the optimized area in 2007.…”

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing

Cited by 17 publications

References 11 publications

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Applications of Vedic multiplier - A Review

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

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