A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

Bae, Woorham; Yoon, Kyung Jean; Song, Taeksang; Nikolić, Borivoje

doi:10.1109/tcsii.2018.2868460

Cited by 10 publications

(8 citation statements)

References 14 publications

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“…The methodology to reliably translate I MAJ into a CMOS compatible voltage is the crucial aspect of the proposed majority gate implementation. We used the sensing method presented by Woorham Bae et al [14,15] which is based on StrongARM latch to sense current difference of the order of a few µA (Figure 5). The current I MAJ from the 1T-1R array is mirrored by N 1 -N 2 pair and compared with I REF in a current mode SA.…”

Section: Sensing Methodologymentioning

confidence: 99%

“…The current I MAJ from the 1T-1R array is mirrored by N 1 -N 2 pair and compared with I REF in a current mode SA. The op-amp biases the drain of transistor N 1 at a constant voltage, V BI AS to ensure that N 1 is in saturation (feedback bias [15]). To read from a cell, V BI AS of 0.8 V was used and 1.1 V was applied at BL, resulting in an effective voltage of 0.3 V (the SL is held at 0.8 V by the op-amp, Figure 5).…”

Section: Sensing Methodologymentioning

confidence: 99%

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Binary Addition in Resistance Switching Memory Array by Sensing Majority

Reuben

2020

Micromachines

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The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.

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Section: Sensing Methodologymentioning

confidence: 99%

Section: Sensing Methodologymentioning

confidence: 99%

Binary Addition in Resistance Switching Memory Array by Sensing Majority

Reuben

2020

Micromachines

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“…On the other hand, some circuit design techniques can be introduced to mitigate the snapback current ( Kim & Ahn, 2005 ; Redaelli et al, 2004 ; Parkinson, 2011 ). Also, circuit designers can propose variation-tolerant or variation-compensated techniques to address the variation issue ( Athmanathan et al, 2016 ; Park et al, 2017 ; Hwang et al, 2010 ; Bae et al, 2018 ), or sneak-current cancellation scheme for the sneak current issue ( Vontobel et al, 2009 ; Shevgoor et al, 2015 ; Bae et al, 2016 ). In addition, looking further forward, RRAM is regarded to be a promising candidate for in-memory computing or neuromorphic computing, because of its capability to store analog weights ( Alibart, Zamanidoost & Strukov, 2013 ; Prezioso et al, 2015 ; Yoo, 2019 ; Xue et al, 2019 ; Kim & Williams, 2019 ; Yoon, Han & Bae, 2020 ; Wang et al, 2019 ).…”

Section: Memory and Storagementioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…In the first stage of sensing, the RRAM's resistance is converted to a current which flows in the N 1 -N 2 current mirror, following the approach of [12]. In a 1T-1R configuration, this is implemented by activating the WL and applying a small voltage (typically <= 0.2 V so that the cell's state is not disturbed) across the cell.…”

Section: A Principlementioning

confidence: 99%

“…In a 1T-1R configuration, this is implemented by activating the WL and applying a small voltage (typically <= 0.2 V so that the cell's state is not disturbed) across the cell. As depicted in Fig.1-(b), the op-amp biases the drain of N 1 at a constant voltage, V BIAS to ensure that N 1 is in saturation (feedback bias [12]). Therefore, transistor pair N 1 −N 2 acts as a current-mirror and I read will be mirrored in N 2 and is available for sensing 1 .…”

Section: A Principlementioning

confidence: 99%

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.

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A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

Cited by 10 publications

References 14 publications

Binary Addition in Resistance Switching Memory Array by Sensing Majority

Binary Addition in Resistance Switching Memory Array by Sensing Majority

Today’s computing challenges: opportunities for computer hardware design

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

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