A variable-radix digit-serial design methodology and its application to the discrete cosine transform

Abstract

A variable-radix digit-serial design methodology and its application to the implementation of a systolic structure for computing the discrete cosine transform is presented. Based on the parameters supplied by a user, different fixed-point designs can be derived from a single floating-point description where tradeoffs among quantization effects, throughput, latency, and area can be addressed. The resulting hardware implementations have variables of different wordlengths and operators of different radices. This design methodology enables efficient exploration of a complex design space to determine the most suitable implementation for a particular application. Index Terms-Design automation, design methodology, discrete cosine transforms, field-programmable gate arrays (FPGAs), fixed-point arithmetic. I. INTRODUCTION T HE discrete cosine transform (DCT), proposed by Ahmed et al. in 1974 [1], has become an increasingly important tool for image and video signal processing applications due to its utility and its adoption in standards such as Joint Photographic Experts Group (JPEG), Moving Picture Experts Group (MPEG), and CCITT H.261 [2]-[4]. Compared with other orthogonal transforms, the performance of the DCT is very similar to the optimal Karhunen-Loeve transform (KLT) for highly correlated data [5], [6]. Its prominence makes hardware implementations important, particularly in high performance and low-power applications. In this paper, we propose a variable-radix digit-serial design methodology and its application to the implementation of the DCT. This methodology allows many different designs to be derived from a single algorithmic description. In particular, tradeoffs among quantization effects, throughput, latency, and area can be addressed and a large and complex design space can be explored to determine the most suitable implementation for a particular application. The resulting hardware implementation is quite different from those produced by human designers since each variable may have a different wordlength and each operator may have a different radix, a task which would be too tedious for most designers. Such a design process poses two main challenges: appropriate wordlengths must be determined for each variable used in the DCT and the radix must be selected for each of the operators subject to user's requirements for throughput, latency, and area [7]. To address the former problem, an opti

Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E

“…Several hardware design methods for the implementation of the 2D DCT have been developed in recent years [7][8][9][10].…”

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

“…Several hardware design methods for the implementation of the 2D DCT have been developed in the recent years [7][8][9][10].…”

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

“…In contrast, our approach is much more compact and therefore enables larger transform sizes at the cost of higher latency. Leong [7] implements a variable radix, bit serial DCT using a systolic array but only describes area requirements for designs up to N=32. In comparison, our approach supports much larger transform sizes with demonstrated designs of up to 1024 points.…”