A unifying framework for systolic designs

Abstract

A systematic methodology to synthesize systolic designs is described and used to derive a new design for dynamic programming. This latter design uses fewer processing elements than previously considered ones. The synthesis method consists of two pans: 1) deriving from the high-level problem specification a form more suitable to VLSI implementation; 2) mapping the new specification into physical hardware. The method also provides a Wlifying framewOIK for existing systolic algorithms.

Parallel implementation of a dynamic programming paradigm

“…Adding the time to solve the min operation c i,j = min i<k<j {f (c i,k , c k,j )}, it results that after O(j − i) time the value c i,j is computed. This is not a new idea [1] but our algorithm implement the pipelining very simple and with low cost of local memory and computation component complexity. In order to pipelining the computation of the c i,j values it is necessary to establish a order on the set of pairs (c i,k , c k,j ), k = i + 1, .…”