A Unified WCET analysis framework for multicore platforms

Chattopadhyay, Sudipta; Chong, Lee Kee; Roychoudhury, Abhik; Kelter, Timon; Marwedel, Peter; Falk, Heiko

doi:10.1145/2584654

Cited by 43 publications

(28 citation statements)

References 31 publications

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“…Most analyses consider multi-core systems with a simple bus providing access to a single shared memory [9], [10], [11], [12]. However, contention analysis of clustered many-core platforms has also been explored, as in [13], [14], [15], [16], where the former two are the most relevant for this work, as they focus on Kalray MPPA-256, which is the platform considered in this paper.…”

Section: Related Workmentioning

confidence: 99%

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

Becker

Dasari

Nicolic

et al. 2016

2016 28th Euromicro Conference on Real-Time Systems (ECRTS)

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Abstract-Next generations of compute-intensive real-time applications in automotive systems will require more powerful computing platforms. One promising power-efficient solution for such applications is to use clustered many-core architectures. However, ensuring that real-time requirements are satisfied in the presence of contention in shared resources, such as memories, remains an open issue.This work presents a novel contention-free execution framework to execute automotive applications on such platforms. Privatization of memory banks together with defined access phases to shared memory resources is the backbone of the framework. An Integer Linear Programming (ILP) formulation is presented to find the optimal time-triggered schedule for the on-core execution as well as for the access to shared memory. Additionally a heuristic solution is presented that generates the schedule in a fraction of the time required by the ILP. Extensive evaluations show that the proposed heuristic performs only 0.5% away from the optimal solution while it outperforms a baseline heuristic by 67%. The applicability of the approach to industrially sized problems is demonstrated in a case study of a software for Engine Management Systems.

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Section: Related Workmentioning

confidence: 99%

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

Becker

Dasari

Nicolic

et al. 2016

2016 28th Euromicro Conference on Real-Time Systems (ECRTS)

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“…Each of the buffers has a capacity of b C flits on the C-NoC, and b D flits on the D-NoC. In contrast to most NoC implementations, links on the KalrayNoC do not have a flow control mechanism [9], [28]. This means a buffer can potentially overflow if more flits arrive than depart over a certain time period.…”

Section: B Switching Mechanism On the Nocmentioning

confidence: 99%

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms.In this work, we target a state-of-the-art many-core processor, the Kalray MPPA. A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis. Abstract-Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip (NoC), which is used for communication among the compute cores via the off-chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. Partitioning and Analysis of theIn this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

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“…Similarly to our work, most analyses consider multi-core systems with a bus providing access to a shared memory with a single port (Schliecker et al 2010;Schliecker and Ernst 2011;Pellizzoni et al 2010;Dasari et al 2011;Dasari and Nelis 2012;Chattopadhyay et al 2014;Rodrigues et al 2013). However, these works are quite different with respect to the considered task models and scheduling policies for both the tasks themselves and their memory requests.…”

Section: Related Workmentioning

confidence: 99%

“…Existing work addresses the problem of deriving upper bounds on memory bus contention, but the analysis is tightly coupled to a particular arbitration policy, such as TDM (Rosén et al2007;Chattopadhyay et al 2010Chattopadhyay et al , 2014Kelter et al 2011;Schranzhofer et al , 2011 or non-specified work-conserving arbiters (Dasari et al 2011;Schliecker et al 2010), and a generic framework to handle different arbitration mechanisms does not exist. As a result, a change of memory arbiter currently implies adopting a new analysis with different inputs and assumptions.…”

Section: Introductionmentioning

confidence: 99%

A framework for memory contention analysis in multi-core platforms

2015

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The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying B Dakshina Dasari 123 Real-Time Syst it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

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A Unified WCET analysis framework for multicore platforms

Cited by 43 publications

References 31 publications

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

A framework for memory contention analysis in multi-core platforms

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