A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS

Bickerstaff, M.; Garrett, David; Prokop, Tomáš; Thomas, Christina; Widdup, B.; Zhou, Ge; Davis, Linda M.; Woodward, Graeme; Nicol, Chris; Yan, Ran

doi:10.1109/jssc.2002.803929

Cited by 74 publications

(20 citation statements)

References 9 publications

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“…In fact, our design could be embedded in the previous design as a co-processor that performs the SISO decoding. As examples of ASIC designs, we have included a unified turbo Viterbi decoder [27] and a very fast SISO decoder [28], which pipelines the add-compareselect kernels. Finally, two commercial IPs are presented in [24] and [29].…”

Section: Previous Work and Comparisonmentioning

confidence: 99%

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Ituero¹,

López-Vallejo²

2008

ETRI Journal

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Pablo Ituero et al.113Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.Keywords: Application specific instruction-set processor (ASIP), maximum a posteriori (MAP), soft-input softoutput (SISO) decoder, software defined radio (SDR), turbo code, very long instruction word (VLIW) architectures.

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Section: Previous Work and Comparisonmentioning

confidence: 99%

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Ituero¹,

López-Vallejo²

2008

ETRI Journal

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“…Mode0 (mode) refers to the task represented by DFG1 and mode1 (not mode) refers to the one represented by DFG2. Actually ld_R 1 and ld_R 2 do not require more logic gates whereas ld_R 3 and ld_R 4 generate extra logic gates (figure 5c). Let us now consider another approach.…”

Section: Problem Formulationmentioning

confidence: 99%

“…The DFG which has the greatest ratio between its number of compatible operations and its throughput constraint is considered as the main DFG. The same rule is applied for ordering the other DGFs (secondary 3 Compatible operations are operations that can be executed using the same type of operator (example 1: additions are compatible each other because they can be executed by an adder; example 2: additions and subtractions are compatible if adder/subtractor multifunction operators are allocated). When all DFGs have been scheduled, operations and variables of the main DFG are bounded to functional units and registers.…”

Section: Design Flowmentioning

confidence: 99%

Synthesis of Multimode digital signal processing systems

Andriamisaina

Casseau

Coussy

2007

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

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“…Low-density parity-check (LDPC), Reed Solomon, Viterbi and Turbo codes are used to meet the growing need to improve the spectrum efficiency [1], [2], [3], [4], [5]. In FEC schemes the encoding of data is done using convolutional encoding and at the receiver end the decoding process is done by viterbi or turbo decoders [21][22][23][24][25][26][27][28][29][30][31]. The viterbi decoder is suitable in wireless communication systems in which the transmitted signals are corrupted by additive white Gaussian noise [6].…”

Section: Introductionmentioning

confidence: 99%

Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

Buzdar¹,

Sun²,

Azhar³

et al. 2017

ijacsa

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Abstract-Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.

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A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS

Cited by 74 publications

References 9 publications

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Synthesis of Multimode digital signal processing systems

Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

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