A Unified NVRAM and TRNG in Standard CMOS Technology

Serrano, Ronaldo; Duran, Ckristian; Sarmiento, Marco; Pham, Cong‐Kha

doi:10.1109/access.2022.3193639

Cited by 5 publications

(4 citation statements)

References 45 publications

(42 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The possibility of switching the I SC polarity can pave the way for a novel self‐powered, non‐volatile memory device, whereas generally, a drain bias of several volts is used for the reading. [ 62 ] Figure 6d illustrates the proposed working principle of such a memory device with electrical writing and photovoltaic reading, where V g = −80 V and V g = +80 V represent a logic “0” and “1,” respectively. Despite the applied gate pulse, there is no output signal in dark conditions due to the absence of I SC .…”

Section: Resultsmentioning

confidence: 99%

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures

Uzhansky,

Mukherjee,

Vijayan

et al. 2023

Adv Funct Materials

View full text Add to dashboard Cite

It is impossible to imagine modern electronic circuitry without a p–n junction—an essential building block for transistors, rectifiers, amplifiers, photovoltaics, etc. Conventional fabrication processes (ion implantation or chemical diffusion) result in an immutable potential configuration depriving reconfigurability. In contrast, the superior electrostatic tunability, dangling bonds‐ and reconstruction‐free interfaces are some of the key features of 2D based heterostructures, making them promising candidates for cutting‐edge optoelectronic and memory applications. Herein, the intercoupled 2D ferroelectricity of 𝛼‐In2Se3 is utilized to introduce micron‐scale, non‐volatile electrostatic doping in ambipolar WSe2, enabling reconfigurable p–n junction. The actuation mechanism is based on the strong polarization field along the edge topology of In2Se3. The fabricated device presents stable p–n to n–p switching, a superior rectification ratio of ≈106, and a low leakage current of ≈10−12 A. Furthermore, the switchable short‐circuit current response is utilized to demonstrate a novel self‐powered, non‐volatile memory based on photovoltaic reading. The ferroelectric non‐volatility coupled with the ability to control the device operation using optical and electrical signals paves the way for ultrathin energy‐efficient, multi‐level optoelectronic and in‐memory logic devices.

show abstract

Section: Resultsmentioning

confidence: 99%

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures

Uzhansky,

Mukherjee,

Vijayan

et al. 2023

Adv Funct Materials

View full text Add to dashboard Cite

show abstract

“…Extensive use of the existing SRAM array infrastructure allows for the integration of the entire key generation subsystem with only a 12.7% increase in area compared to a baseline SRAM [157]. The study, introduced a unified NVRAM-TRNG that employs high-voltage transistors to withstand the voltage requirements during the program and erase operations in NVRAM mode [158]. To capture jitter noise utilizes a single ring oscillator (RO) divided into two interconnected stages.…”

Section: A Hardware Security Modules: 1) True Random Number Generator...mentioning

confidence: 99%

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

View full text Add to dashboard Cite

To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.

show abstract

“…The balanced latches are used for a TRNG application. However, the process variations impose problems when balancing the latch, which require a calibration step [7,20,21]. On the other hand, the unbalanced latches produce a stable and unique response.…”

Section: Physical Phenomenamentioning

confidence: 99%

“…For example, a static random access memory (SRAM) can be used to generate a TRNG-PUF, exploiting the bit line's time response and leakage current [4][5][6]. In addition, a TRNG and a non-volatile random access memory (NVRAM) can be unified, exploiting the metastability in the sense amplifier [7] or reading the bit cell noise [8]. On the other hand, a PUF-NVRAM is unified using the initial charges into the floating gates' bit cells [9].…”

Section: Introductionmentioning

confidence: 99%

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

et al. 2022

Self Cite

View full text Add to dashboard Cite

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation.

show abstract

A Unified NVRAM and TRNG in Standard CMOS Technology

Abstract: This work is based on results obtained from a project JPNP16007, commissioned by the New Energy and Industrial Technology Development Organization (NEDO).

Cited by 5 publications

References 45 publications

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Contact Info

Product

Resources

About

A Unified NVRAM and TRNG in Standard CMOS Technology

Abstract: This work is based on results obtained from a project JPNP16007, commissioned by the New Energy and Industrial Technology Development Organization (NEDO).

Cited by 5 publications

References 45 publications

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe2/α‐In2Se3 Asymmetric Heterostructures

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe2/α‐In2Se3 Asymmetric Heterostructures

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Contact Info

Product

Resources

About

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe₂/α‐In₂Se₃ Asymmetric Heterostructures