A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

Jiang, Hongwu; Huang, Shanshi; Peng, Xiaochen; Su, Jian‐Wei; Chou, Yen-Chi; Huang, Wei-Hsing; Liu, Chun‐Jen; Liu, Ruhui; Chang, Meng‐Fan; Yu, Shimeng

doi:10.1109/dac18072.2020.9218524

Cited by 27 publications

(8 citation statements)

References 22 publications

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“…In DNN+NeuroSim V2.0, we do not consider pipeline among the four key steps in training, i.e. #1 feed-forward, #2 computation of error, #3 computation of weight gradient, and #4 weight update, but the users can potentially optimize the design as done in other works [14] [15]. However, the framework provides an option to build up pipeline system for feed-forward and computation of error, as we assume all the weights are stored on-chip in CIM synaptic arrays, we can process multiple images simultaneously on-chip, i.e.…”

Section: Cim Architecture For Trainingmentioning

confidence: 99%

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Peng

Huang

Luo

et al. 2019

2019 IEEE International Electron Devices Meeting (IEDM)

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221

105

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DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from devicelevel, to circuit-level and up to algorithm-level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior work (open-source framework DNN+NeuroSim V1.1: https://github.com/neurosim/DNN_NeuroSim_V1.1) was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of inference engines. In this work, we further investigated the impact of the "analog" emerging non-volatile memory (eNVM)'s non-ideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The proposed DNN+NeuroSim V2.0 framework is available on GitHub at https://github.com/neurosim/DNN_NeuroSim_V2.0.

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Section: Cim Architecture For Trainingmentioning

confidence: 99%

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Peng

Huang

Luo

et al. 2019

2019 IEEE International Electron Devices Meeting (IEDM)

Self Cite

221

105

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“…SRAM is a kind of volatile memory, which has the advantages of fast access speed, low static power consumption, and high durability, and is a common memory for CIM. Currently, SRAM-CIM can be divided into AD-CIM [1][2] [3] [4], DD-CIM [5], and TD-CIM [6][7] [8] according to the calculation method.…”

Section: Introductionmentioning

confidence: 99%

DominoCIM: A 28nm 138.04TOPS/W Spike-Domain Computing-in-Memory 6T-SRAM Macro for AI and Embedded Applications

Zhang

et al. 2023

J. Phys.: Conf. Ser.

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The realization of computing in memory based on SRAM(SRAM-CIM) can be divided into three domains: analog domain (AD-CIM), time domain (TD-CIM), and digital domain (DD-CIM). However, there exist corresponding disadvantages to the above methods. For AD-CIM, the calculation accuracy is poor. Moreover, the output stability of TD-CIM is limited. With a large overhead area, the layout and wiring of DD-CIM are complicated. Aiming to solve the shortcomings, this paper proposes a spike-domain circuit based on a pulse edge counting scheme. The circuit uses digital logic to realize the MAC operation, which is less affected by power, voltage, and temperature (PVT) and performs higher calculation accuracy. The circuit is transmitted serially through the delay chain to achieve a smaller area overhead. At 28 nm, the circuit accomplishes energy efficiency (EF) with 138.04TOPS/W for 4-bit multiplication and addition (MAC) operations, enabling full precision output and 3.42 times less energy consumption per operation than the previous SRAM-CIM.

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“…RECOM [ 24 ] was the first CIM-based accelerator to support DNN processing. Jiang et al [ 25 , 26 ] proposed SRAM CIM accelerators for CNN training. However, in several cases, it was assumed that the CIM macros were in the ideal state.…”

Section: Introductionmentioning

confidence: 99%

SRAM-Based CIM Architecture Design for Event Detection

Sulaiman¹,

Lin²,

Li³

et al. 2022

Sensors

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Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the high computational complexity and high-energy consumption of CNNs trammel their application in hardware accelerators. Computing-in-memory (CIM) is the technique of running calculations entirely in memory (in our design, we use SRAM). CIM architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. CIM-based architecture for event detection is designed to trigger the next stage of precision inference. To implement an SRAM-based CIM accelerator, a software and hardware co-design approach must consider the CIM macro’s hardware limitations to map the weight onto the AI edge devices. In this paper, we designed a hierarchical AI architecture to optimize the end-to-end system power in the AIoT application. In the experiment, the CIM-aware algorithm with 4-bit activation and 8-bit weight is examined on hand gesture and CIFAR-10 datasets, and determined to have 99.70% and 70.58% accuracy, respectively. A profiling tool to analyze the proposed design is also developed to measure how efficient our architecture design is. The proposed design system utilizes the operating frequency of 100 MHz, hand gesture and CIFAR-10 as the datasets, and nine CNNs and one FC layer as its network, resulting in a frame rate of 662 FPS, 37.6% processing unit utilization, and a power consumption of 0.853 mW.

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

Cited by 27 publications

References 22 publications

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

DominoCIM: A 28nm 138.04TOPS/W Spike-Domain Computing-in-Memory 6T-SRAM Macro for AI and Embedded Applications

SRAM-Based CIM Architecture Design for Event Detection

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