A Triple-Band Voltage-Controlled Oscillator Using Two Shunt Right-Handed 4^th-Order Resonators

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

“…The promoted divider loop consists of a CML divider, a differential to single circuit, a true single-phase clock (TSPC) divider and a MMD to achieve the divide ratio 104, as shown in Figure 6 b [ 14 ]. The CML divider circuit is used to handle the higher frequency of the VCO [ 15 , 16 ] output signal and produces divide-by-2 signal. The circuit of differential to single-ended sends the output signal of CML to the TSPC divider, and then produces the divide-by-2.…”