A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units

Middha, Bhuvan; Raj, V.; Gangwar, Anup; Kumar, Anshul; Balakrishnan, M.; Ienne, Paolo

doi:10.1145/581199.581203

Cited by 17 publications

(5 citation statements)

References 5 publications

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“…Figure 2 shows the methodology that we have applied. Firstly, the target ap- plication is simulated by Trimaran [29], a tool widely applied to obtain multiple metrics during running applications. Similarly, energy consumption per access is computed by CACTI [30], which is a well-known cache simulator used for estimating energy consumption for different processor structures.…”

Section: Register File Optimizationmentioning

confidence: 99%

Evolutionary Design of the Memory Subsystem

Álvarez,

Risco-Martín,

Colmenar

2023

Preprint

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The memory hierarchy has a high impact on the performance and power consumption in the system. Moreover, current embedded systems, included in mobile devices, are specifically designed to run multimedia applications, which are memory intensive. This increases the pressure on the memory subsystem and affects the performance and energy consumption. In this regard, the thermal problems, performance degradation and high energy consumption, can cause irreversible damage to the devices.We address the optimization of the whole memory subsystem with three approaches integrated as a single methodology. Firstly, the thermal impact of register file is analyzed and optimized. Secondly, the cache memory is addressed by optimizing cache configuration according to running applications and improving both performance and power consumption. Finally, we simplify the design and evaluation process of general-purpose and customized dynamic memory manager, in the main memory. To this aim, we apply different evolutionary algorithms in combination with memory simulators and profiling tools. This

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Section: Register File Optimizationmentioning

confidence: 99%

Evolutionary Design of the Memory Subsystem

Álvarez,

Risco-Martín,

Colmenar

2023

Preprint

View full text Add to dashboard Cite

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“…The scope of the code covered by an identified CI candidate varies from very fine-grained-inside a basic block-to across basic blocks. There are two types of very fine grained CIs: multiple input single output (MISO) and multiple input multiple output (MIMO) CIs [Middha et al 2002]. Several previous works [Atasu et al 2003;Yu and Mitra 2004;Pozzi et al 2006] extract these kinds of CIs, which are DAG subgraphs always found within a basic block.…”

Section: Related Workmentioning

confidence: 99%

MInGLE

Gonzalez-Alvarez

Sartor

Álvarez

et al. 2016

ACM Trans. Archit. Code Optim.

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The end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more efficiently, optimizing not only for performance but also for power. However, hardware specialization for each application is costly and impractical due to time-to-market constraints. Domain-specific specialization is an alternative that can increase hardware reutilization across applications that share similar computations. This article explores the specialization of low-power processors with custom instructions (CIs) that run on a specialized functional unit. We are the first, to our knowledge, to design CIs for an application domain and across basic blocks, selecting CIs that maximize both performance and energy efficiency improvements. We present the Merged Instructions Generator for Large Efficiency (MInGLE), an automated framework that identifies and selects CIs. Our framework analyzes large sequences of code (across basic blocks) to maximize acceleration potential while also performing partial matching across applications to optimize for reuse of the specialized hardware. To do this, we convert the code into a new canonical representation, the Merging Diagram, which represents the code’s functionality instead of its structure. This is key to being able to find similarities across such large code sequences from different applications with different coding styles. Groups of potential CIs are clustered depending on their similarity score to effectively reduce the search space. Additionally, we create new CIs that cover not only whole-body loops but also fragments of the code to optimize hardware reutilization further. For a set of 11 applications from the media domain, our framework generates CIs that significantly improve the energy-delay product (EDP) and performance speedup. CIs with the highest utilization opportunities achieve an average EDP improvement of 3.8 × compared to a baseline processor modeled after an Intel Atom. We demonstrate that we can efficiently accelerate a domain with partially matched CIs, and that their design time, from identification to selection, stays within tractable bounds.

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“…When designing VLIW ASIPs, simultaneously satisfying the tight constraints of delay, area, and power consumption is required. For this purpose, design space exploration should be performed to determine the optimal architecture parameters of VLIW ASIPs 2), 3) . One of the main concerns is that design space exploration is time consuming.…”

Section: Introductionmentioning

confidence: 99%

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions

Iwato

Sakanushi

Takeuchi

et al. 2010

IPSJ Transactions on System LSI Design Methodology

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This paper proposes a low-power ASIP generation method by automatically extracting minimum execution conditions of pipeline registers for clock gating. For highly effective power reduction by clock gating, it is important to create minimum execution conditions, which can shut off redundant clock supplies for registers. To automatically extract the conditions, our proposed method employs micro-operation descriptions (MODs) that specify ASIP architecture. Utilizing MODs through the ASIP generation processes, our proposed method automatically extracts the minimum execution conditions. Experimental results show that the power consumption of the pipeline registers in ASIPs generated with the proposed method is reduced about 80% compared to ASIPs that are not clock gated, and about 60% compared to ASIPs that are clock gated by Power Compiler with negligible delay and area overhead.

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A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units

Cited by 17 publications

References 5 publications

Evolutionary Design of the Memory Subsystem

Evolutionary Design of the Memory Subsystem

MInGLE

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions

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