A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems

Ghiribaldi, Alberto; Bertozzi, Davide; Nowick, Steven M.

doi:10.7873/date.2013.079

Cited by 47 publications

(54 citation statements)

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“…pipelines with forks and joins), also supported by Mousetrap, a more careful analysis and planning is necessary. For example, Figure 3 shows a fragment of the control logic for the bundled-data circular FIFO proposed in [6]. In this circuit, the phase select i signal must propagate to the input pin of latch full reg before req i does -that is, following the RTC naming, phase select i behaves as the data signal, and req i as the control signal.…”

Section: A Relative Timing Constraints (Rtcs)mentioning

confidence: 99%

“…Ghiribaldi et al [6], describe the design and synthesis of an asynchronous BD network on chip router, starting from a lowlevel asynchronous RTL description. Circuit optimization and delay matching take place during logic synthesis.…”

Section: Related Workmentioning

confidence: 99%

“…The automatic insertion of buffers in synthesis tools can overcome Challenge 1 and different works have exploited it in the past [6], [9], [11], [12]. Also, techniques similar to those explored for clock distribution in synchronous designs, like the works presented in [13], [14], are useful to cope with Challenge 1.…”

Section: Introductionmentioning

confidence: 96%

“…BD promises to reduce power and increase performance at area/power costs similar to those of synchronous circuits [5], [6]. BD templates are thus increasingly popular [6]- [8], and different schemes exist for their implementation, e.g. desynchronization [9], Mousetrap [10] and Blade [8].…”

Section: Introductionmentioning

confidence: 99%

“…Generally speaking, QDI provides more relaxed timing assumptions, but its cost in terms of area and power can be prohibitively high for many applications. BD promises to reduce power and increase performance at area/power costs similar to those of synchronous circuits [5], [6]. BD templates are thus increasingly popular [6]- [8], and different schemes exist for their implementation, e.g.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

Gibiluka

Moreira

Calazans

2015

2015 Euromicro Conference on Digital System Design

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Contemporary silicon technology enables integrating billions of transistors and allows the creation of complex systems-on-chip. At the same time, strict power dissipation budgets and growing interest in high performance battery-powered devices drive the need for energy-efficient high performance circuits. Bundled-data asynchronous circuits are good candidates for high performance low power systems, as they operate with average-case delays and present reduced switching activity when compared to other asynchronous templates. The correct operation of bundled-data circuits relies on constraints that describe the timing relationships between data and control signals. However, commercial EDA frameworks do not offer an encompassing support to ensure the closure of such constraints, making implementation challenging. This paper proposes a synthesis flow to enable the description and enforcement of relative timing constraints at both logic and physical synthesis levels, using the Synopsys framework and a set of in-house scripts. Two case studies illustrate the flow: a pipelined multiplier and a network on chip input buffer FIFO, the latter comprising a non-linear pipeline and complex control circuits. Both case studies target the STMicroelectronics 28nm FDSOI technology, and validation occurs with post-layout simulations. Overall, the flow provides an automatic approach to meet relative timing constraints in a template-agnostic manner for bundled-data circuits design.

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Section: A Relative Timing Constraints (Rtcs)mentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%