A transimpedance amplifier for optical communication network based on active voltage-current feedback

Seifouri, Mahmood; Amiri, Parviz; Dadras, Iman

doi:10.1016/j.mejo.2017.07.003

Cited by 33 publications

(15 citation statements)

References 17 publications

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“…The proposed TIA in this paper has half the bandwidth reported in Seifouri et al and about 10 times less transimpedance gain but benefits from consuming 95% less power with higher input capacitance and less input referred noise. Moreover, the proposed TIA in this paper consumes the lowest power, while the input capacitance is relatively large in comparison with other references in Table , and the performance of the noise is better than circuits reported in the literature . These characteristics are obtained in cost of obtaining a narrower bandwidth and less transimpedance gain.…”

Section: Simulation Resultsmentioning

confidence: 87%

“…In the recent years, researchers have discussed and analyzed different circuit structures and techniques to improve the performance of the TIA circuits for using in high‐speed communication applications. These techniques are as follows: f T doubler, shunt peaking, inductive peaking and series peaking technique, active feedback, 3D inductor serial peaking, slew boosting, Regulated Cascode (RGC), common‐drain feedback, T‐coil inductor matching, negative impedance compensation, double three‐order active feedback, stagger tuning, Л‐network, voltage‐current feedback, the zero and pole cancellation, and a three‐dimensional inductor converter . In addition, structures that are usually used as TIA building blocks to alleviate the bandwidth reduction are as follows: RGC structure, stagger tuning, and T‐coil inductor matching.…”

Section: Introductionmentioning

confidence: 99%

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A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

Zohoori

Dolatshahi

2018

Circuit Theory & Apps

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In this paper, a modified Regulated Cascode (RGC)-based, low-power, transimpedance amplifier (TIA) is proposed followed by a closed-loop gain stage beside an added level shifter circuit to the booster of a conventional RGC circuit to set the proper biasing conditions for the transistors in the proposed TIA structure in 90-nm CMOS technology. Moreover, the added gain stage benefits from an active inductor which resonates with the output capacitance of the TIA circuit to extend the bandwidth while saves the occupied chip area in comparison with passive inductor schemes. In addition, the performance of the proposed TIA circuit is simulated in HSPICE using 90-nm CMOS technology parameters which show a transimpedance gain of 41 dBΩ, −3-dB frequency bandwidth of 3.7 GHz, input referred noise value of 834nA rms , and the power consumption value of only 1.4 mW at 1-V supply.

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Section: Simulation Resultsmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

Zohoori

Dolatshahi

2018

Circuit Theory & Apps

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“…It is seen that the bandwidth and power dissipation of the proposed TIA are better than other TIA designs except. 1,6 However, the bandwidth of designs in 1,6 is high but at the cost of a larger chip area. The designs presented in 15,21 occupy a lesser area than the proposed TIA but these designs dissipate more power.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…The main design limitation of TIA is to achieve wide bandwidth because of its input photodiode capacitance. Several design techniques have been reported to relax this parasitic effect such as inductive peaking, [1][2][3][4][5][6][7] inductive feedback, 8 common-gate (CG) input configuration, 9,10 regulated cascode (RGC), [11][12][13] negative impedance, 14,15 capacitive feedback, 16,17 capacitive degeneration, 18,19 multi-path TIAs, 20 and shunt feedback. 21 The inductive peaking technique is commonly used to increase the bandwidth, which inevitably increases the chip area consumption.…”

Section: Introductionmentioning

confidence: 99%

Wideband inductorless transimpedance amplifier using capacitive degeneration and negative capacitance

Singh

Gupta

2020

Int J Numerical Modelling

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This paper presents a new wideband inductorless CMOS transimpedance amplifier (TIA) for 10Gb/s applications. In this proposed TIA, inverter-based common-drain active feedback topology is modified by introducing a cascode transistor to reduce input impedance. Furthermore, capacitive degeneration and negative capacitance techniques are employed by using a single capacitor. Both techniques extend the bandwidth. Mathematical analysis of the proposed TIA has been done using the small signal model to describe bandwidth extension. To verify the theoretical description, the proposed TIA is simulated using TSMC 0.18 μm CMOS technology at 1.8 V power supply with 4.3 mW power consumption. The input photodiode capacitance is 0.25 pF. Simulation results show the transimpedance gain of 51.4 dBΩ and 7.6 GHz bandwidth. The input noise current spectral density is 27 pA/√Hz.

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“…In this work, active voltage-current feedback TIA topology [15] is used which provides low input and output impedances. In this topology, thegain enhancing pathis introduced insuch a way that it increases both gain and bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Wideband High Gain Active Feedback Transimpedance Amplifier

Singh

Gupta

Aggrawal

et al. 2021

Preprint

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This paper presents a new wideband high gain CMOS transimpedance amplifier without using any inductor. In the proposed TIA, gain enhancing path is introduced in the active voltage-current feedback TIA topology to increase both the gain and bandwidth. This path increases the transconductance of the proposed TIA which reduces the input resistance and leads to bandwidth extension. Additionally, for utilizing the benefit of this topology, cascading of common source stage is also done to increase the gain further without deteriorating the bandwidth. Mathematical analysis is also performed to evaluate both the gain and bandwidth enhancement. These analyses are supported by simulations that are done using TSMC 180 nm CMOS technology with the input photodiode capacitance of 0.3 pF. The proposed TIA occupies 0.019 mm2 area and consumes 3.2 mW from the power supply of 1.8 V. Simulation results show that the transimpedance gain of the proposed TIA is 57.15 dBΩ over the bandwidth of 6.5 GHz. The input noise is 17.16 pA/√Hz.

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A transimpedance amplifier for optical communication network based on active voltage-current feedback

Cited by 33 publications

References 17 publications

A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

Wideband inductorless transimpedance amplifier using capacitive degeneration and negative capacitance

Wideband High Gain Active Feedback Transimpedance Amplifier

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