A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application

Liu, Nanqi; Johnson, Brian; Nadig, Vinay; Chen, Degang

doi:10.1109/iscas.2018.8351236

Cited by 16 publications

(7 citation statements)

References 11 publications

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“…This circuit is stable. Tsettle is the recovery time when VOUT settles back to 1% accuracy [33]. As shown in Figure 11, the undershoot, overshoot and recovery time of the LDO without the proposed dynamic bias circuit were about 248 mV, 260 mV and 177 ns, respectively, while those of the LDO with the proposed circuit were about 242 mV, 250 mV and 52 ns only, respectively.…”

Section: Simulation Resultsmentioning

confidence: 97%

“…The max overshoot was 283 mV at 85 °C in the SS corner, while the min overshoot was 217 mV at −40 °C in the FS corner. The max undershoot was 280 mV at 85 °C in the SS corner, and the min undershoot T settle is the recovery time when V OUT settles back to 1% accuracy [33]. As shown in Figure 11, the undershoot, overshoot and recovery time of the LDO without the proposed dynamic bias circuit were about 248 mV, 260 mV and 177 ns, respectively, while those of the LDO with the proposed circuit were about 242 mV, 250 mV and 52 ns only, respectively.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This circuit realized bias current change in load changes, but the capacitor consumed a greater area. The authors of [33] proposed a novel positive transient detection circuit to improve the transient response, but the better effect was achieved only with heavy to light load changes. This paper proposes a dynamic bias generation circuit for fast charging/discharging of the large gate-source parasitic capacitance of the power transistor M P by using an MOS to detect changes in the output.…”

Section: Proposed Dynamic Bias Circuitmentioning

confidence: 99%

See 2 more Smart Citations

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Chen

Wang

et al. 2022

Electronics

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The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

show abstract

Section: Simulation Resultsmentioning

confidence: 97%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Proposed Dynamic Bias Circuitmentioning

confidence: 99%

See 1 more Smart Citation

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Chen

Wang

et al. 2022

Electronics

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“…Typically, the pass transistor of the LDO regulator is designed to be as sizable as possible. This indicates that the pass transistor has the most superior current driving capability among the LDO regulators [8]. Hence, the proposed LDO regulator was designed to effectively control the load current by discharging and supplying additional current to the gate node of the pass transistor [9].…”

Section: Proposed Ldo Regulator With Transient Current-sensing Structurementioning

confidence: 99%

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

et al. 2023

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In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

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“…The efficiency of DC-DC converters can reach more than 90% [1,2,3,4,5,6,7,8,9]. However, its large output ripple limits its applications in sensitive electronic load where additional LDO is required to achieve low power noise and ripple [10,11,12,13,14,15,16,17,18,19]. Hybrid methods of switched-mode, switched-capacitor-mode DC-DC, low dropout voltage regulator (LDO) are proposed in recent years [20,21,22,23,24].…”

Section: Introductionmentioning

confidence: 99%

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

Zhou

Min

Luo

2021

IEICE Electron. Express

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Presented is a new type of DC-DC converter and low dropout voltage regulator (LDO) cascaded circuit, which has improved dynamic response and loop stability. In this novel cascaded circuit, the gate voltage of the pass element of the LDO is quantized and compared with a target value to form an error value to finally control the feedback coefficient of the DC-DC converter. Meanwhile, the adjusting speed of this feedback coefficient can be changed dynamically through the gain compensator, which is minimized to obtain the best loop stability when approaching the steady-state and increased to achieve a fast transient response during large dynamic change. The testing results of the prototype designed to verify the feasibility show that the novel cascaded circuit can increase the response speed by 22 times and optimize the voltage ripple by 1.9 times.

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A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application

Cited by 16 publications

References 11 publications

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

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