A transaction-based unified simulation/emulation architecture for functional verification

Kudlugi, Murali; Hassoun, Soha; Selvidge, Charles; Pryor, Duaine

doi:10.1145/378239.379036

Cited by 25 publications

(5 citation statements)

References 10 publications

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“…Note that C-level modeling usually sacrifices timing accuracy in some degree to achieve the faster simulation speed. Murali [5] proposed a verification framework by using a C simulator that drives stimulus for an RTL circuit. Whereas Murali deals with the signal conversion from C-level to RTL, we are focusing on the clock cycle accuracy of the C-level model compared to RTL model.…”

Section: More Details Are Discussed In Section IIImentioning

confidence: 99%

Cycle error correction in asynchronous clock modeling for cycle-based simulation

Lee¹,

Yi²

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy.

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Section: More Details Are Discussed In Section IIImentioning

confidence: 99%

Cycle error correction in asynchronous clock modeling for cycle-based simulation

Lee¹,

Yi²

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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“…The test is res- There are some good references on the subject of transaction based verification [2], [10]. Some commercial tools also deploy the transaction methodology as part of their offerings[14].…”

Section: There Is a Clean Division Between The Tests In A Transactionmentioning

confidence: 99%

“…There are many good examples and discussion of this code in [9] and [10]. The approach indicated is not the only way to address the register programming problem.…”

Section: Addressmentioning

confidence: 99%

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Effective Functional Verification

2006

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All Rights Reserved © 2006 SpringerNo part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.Printed in the Netherlands. This book is dedicated to:The Almighty, who gave me a variety of experiences and the inspiration to write this work. My family for putting up with me as I wrote this book.My colleagues who taught me what they knew and worked with me.

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“…This method has two notable drawbacks: a) the use of text files could be very time-consuming, and b) the method is only applicable to VHDL models. A transaction-based layered architecture waspresented in [12] to speed up functional verification. between the simulator and the emulator.…”

Section: Introductionmentioning

confidence: 99%

Speedup analysis in simulation-emulation co-operation

Miremadi

Sarmadi

Asadi

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach us compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only the simulation part of the simulation-emulation co-operation is used, the speedup is higher than when the pure simulation is used. The total speedup i s also depended on the type of applicdtion instructions and the communication cycle time between the simulator and the emulator.

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A transaction-based unified simulation/emulation architecture for functional verification

Cited by 25 publications

References 10 publications

Cycle error correction in asynchronous clock modeling for cycle-based simulation

Cycle error correction in asynchronous clock modeling for cycle-based simulation

Effective Functional Verification

Speedup analysis in simulation-emulation co-operation

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