A Timed Rewriting Logic Semantics for SDL: A Case Study of the Alternating Bit Protocol

Steggles, LJ; Kosiuczenko, Piotr

doi:10.1016/s1571-0661(05)82554-x

Cited by 9 publications

(4 citation statements)

References 15 publications

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“…This question has been investigated by several authors from two related perspectives. On the one hand, an extension of rewriting logic called timed rewriting logic has been investigated, and has been applied to several examples and specification languages [273,274,366,429]. On the other hand, Ölveczky and I found a simple way to express real-time and hybrid system specifications directly in rewriting logic [359,367,368,371].…”

Section: Real-time Rewrite Theoriesmentioning

confidence: 99%

Twenty years of rewriting logic

Meseguer

2012

The Journal of Logic and Algebraic Programming

160

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Rewriting logic is a simple computational logic that can naturally express both concurrent computation and logical deduction with great generality. This paper provides a gentle, intuitive introduction to its main ideas, as well as a survey of the work that many researchers have carried out over the last twenty years in advancing: (i) its foundations; (ii) its semantic framework and logical framework uses; (iii) its language implementations and its formal tools; and (iv) its many applications to automated deduction, software and hardware specification and verification, security, real-time and cyber-physical systems, probabilistic systems, bioinformatics and chemical systems.

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Section: Real-time Rewrite Theoriesmentioning

confidence: 99%

Twenty years of rewriting logic

Meseguer

2012

The Journal of Logic and Algebraic Programming

160

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“…Rewriting logic can be extended to deal with continuous real-time models. Such an extension, called "Timed rewriting logic" has been investigated, and applied to several examples and specification languages [17,26,27]. In this approach the time is somehow built in the logic.…”

Section: Introductionmentioning

confidence: 99%

Verification of Timed Automata Using Rewrite Rules and Strategies

Beffara,

Bournez,

Kacem

et al. 2009

Preprint

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ELAN is a powerful language and environment for specifying and prototyping deduction systems in a language based on rewrite rules controlled by strategies. Timed automata is a class of continuous real-time models of reactive systems for which efficient model-checking algorithms have been devised. In this paper, we show that these algorithms can very easily be prototyped in the ELAN system. This paper argues through this example that rewriting based systems relying on rules and strategies are a good framework to prototype, study and test rather efficiently symbolic model-checking algorithms, i.e. algorithms which involve combination of graph exploration rules, deduction rules, constraint solving techniques and decision procedures.

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“…The Stop-and-Wait protocol and some of its closely related variants have been checked formally for functional verification using theorem proving [7], state-based formal approaches [4,12,35] and a combination of both techniques [22] and their performance has been analyzed using a number of innovative state-based formal or semi-formal techniques (e.g. [15,30,33,37]). But like other real-time systems, to the best of our knowledge, there is no mechanized approach reported in the literature that utilizes a single model of the Stop-andWait protocol and could verify its functional correctness and precisely analyze its performance.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis and Functional Verification of the Stop-and-Wait Protocol in HOL

Hasan

Tahar

2008

J Autom Reasoning

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Real-time systems usually involve a subtle interaction of a number of distributed components and have a high degree of parallelism, which makes their performance analysis quite complex. Thus, traditional techniques, such as simulation, or the state-based formal methods usually fail to produce reasonable results. In this paper, we propose to use higher-order-logic (HOL) theorem proving for the performance analysis of real-time systems. The idea is to formalize the real-time system as a logical conjunction of HOL predicates, whereas each one of these predicates define an autonomous component or process of the given real-time system. The random or unpredictable behavior found in these components is modeled as random variables. This formal specification can then be used in a HOL theorem prover to reason about both functional and performance related properties of the given realtime system. In order to illustrate the practical effectiveness of our approach, we present the analysis of the Stop-and-Wait protocol, which is a classical example of real-time systems. The functional correctness of the protocol is verified by proving that the protocol ensures reliable data transfers. Whereas, the average message delay relation is verified in HOL for the sake of performance analysis. The paper includes the protocol's formalization details along with the HOL proof sketches for the major theorems.

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A Timed Rewriting Logic Semantics for SDL: A Case Study of the Alternating Bit Protocol

Cited by 9 publications

References 15 publications

Twenty years of rewriting logic

Twenty years of rewriting logic

Verification of Timed Automata Using Rewrite Rules and Strategies

Performance Analysis and Functional Verification of the Stop-and-Wait Protocol in HOL

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