The time slot interchanger (TSI) is employed widely in practice as the switch fabric of digital cross‐connect systems or exchange systems in the digital synchronized network. With the increasing need for ISDN with the fundamental rate of 64 kbit/s as the background, it is desired to realize a large‐capacity TSI. This paper discusses the optimum design of the pipelined TSI which has been proposed in the past, aiming at the realization of a large‐capacity TSI.
First, the TSI configuration is proposed which realizes the time slot integrity in multislot connection, which has been a problem in the traditional pipelined TSI. The proposed method corresponds to the traditional TSI using RAM, where the time slot sequence integrity is realized by employing the double‐buffer structure.
Then the optimum design method for the proposed pipelined TSI is presented, where the evaluation measure is the performance index, defined as the product of memory capacity and the operation speed. For comparison based on the defined performance index, the pipelined TSI optimized by the proposed method has several tens to several hundred times better performance than the conventional TSI using RAM or shift registers. Thus, it is demonstrated that the proposed construction is effective in realizing a large‐capacity TSI.