A tightly-coupled processor-network interface

Henry, Dana S.; Joerg, Christopher F.

doi:10.1145/143371.143497

Cited by 10 publications

(13 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With persistent stream links and these instructions added to the processor's ISA, there is no need to spend extra cycles setting up a communication, specifying the destination, or formating a packet (for contrast, compare e.g., [35,20]). This approach integrates streaming communication into the processor abstraction, allowing it to be supported efficiently with hardware.…”

Section: Stream Opsmentioning

confidence: 99%

Stream computations organized for reconfigurable execution

DeHon

Markovsky

Caspi

et al. 2006

Microprocessors and Microsystems

View full text Add to dashboard Cite

Section: Stream Opsmentioning

confidence: 99%

Stream computations organized for reconfigurable execution

DeHon

Markovsky

Caspi

et al. 2006

Microprocessors and Microsystems

View full text Add to dashboard Cite

“…Registermapped network interfaces have been used previously in the Mars Machine [2], J-Machine, and iWarp [4], and have been described by *T [26] as well as Henry and Joerg [15]. However, none of these systems provide protection for user-level messages.…”

Section: Sor With a Pipelined Fpu (400m(mentioning

confidence: 99%

The M-machine multicomputer

Fillo

Keckler

Dally

et al. 1997

Int J Parallel Prog

View full text Add to dashboard Cite

Because of the increasing density of VLSI integrated circuits, most of the chip area of modern computers is now occupied by memory and not by processing resources. The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by these constraints of modern semiconductor technology and the demands of programming systems, such as faster execution of fixed sized problems and easier programmability of parallel computers. Advances in VLSI technology have resulted in computers with chip area dominated by memory and not by processing resources. The normalized area (in ( 2 ) of a VLSI chip 1 is increasing by 50% per year, while gate speed and communication bandwidth are increasing by 20% per year [14]. As a result, a 64-bit proces- sor with a pipelined FPU (400M(2 ) 2 is only 8% of a 5G( 2 1996 0.355 m chip. In a system with 256 MBytes of DRAM, the processor accounts for 0.13% of the silicon area in the system. The memory system, cache, TLB, controllers, and DRAM account for most of the remaining area. Technology scaling has made the memory, rather than the processor, the most area-consuming resource in a computer system.To address this imbalance, the M-Machine increases the fraction of chip area devoted to processor, making better use of the critical memory resources. An M-Machine multi-ALU processor (MAP) chip contains four 64-bit three-issue clusters that comprise 32% of the 5G( 2 chip and 11% of an 8 MByte (six-chip) node. The multiple execution clusters will provide better peak performance than using a single cluster and a large on-chip cache in the same chip area. The high ratio of arithmetic bandwidth to memory bandwidth (12 operations/word) allows the MAP to saturate the costly DRAM bandwidth even on code with high cache-hit ratios. A 32-node M-Machine system with 256 MBytes of memory has 128 times the peak performance of a 1996 uniprocessor with the same memory capacity at 1.5 times the area, a 85:1 improvement in peak performance/area. Even at a small fraction of this peak performance, such a machine allows the costly, fixed-sized memory to handle more problems per unit time resulting in more cost-effective computing.The M-Machine is intended to extract more parallelism from problems of a fixed size, rather than requiring enormous problems to achieve peak performance. To do this, nodes are designed to manage parallelism at a variety of granularities, from the instruction level to the process level. The 12 function units in a single M-Machine node are controlled using a form of Processor Coupling [18] to exploit instruction level parallelism by executing 12 operations from the same thread, or to exploit thread-level parallelism by executing operations from up to six different threads. The fast internode communication allows collaborating threads to reside on different nodes.The M-Machine also addresses the demand for easier programmability by providing an incremental path for increasing parallelism and performance. An unmodified sequential program can 2 Area was determ...

show abstract

“…The dispatch register combines a user-specified base address with status information to form a program counter [21]. The status portion of the PC forms an index into a code table, much like a processor trap vector table.…”

Section: 'Andphoon-omentioning

confidence: 99%

Decoupled hardware support for distributed shared memory

Reinhardt

Pfile

Wood

1996

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

This paper investigates hardware support for fine-grain distributed shared memory (DSM) in networks of workstations.To reduce design time and implementation cost relative to dedicated DSM systems, we decouple the functional hardware components of DSM support, allowing greater use of off-the-shelf devices.We present two decoupled systems, Typhoon-O and Typhoon-1. Typhoon-O uses an off-the-shelf protocol processor and network interface; a custom access control device is the only DSM-specific hardware. To demonstrate the feasibility and simplicity of this access control device, we designed and built au FPGA-based version in under one year. Typhoon-1 also uses an off-the-shelf protocol processor, but integrates the network interface and access control devices for higher performance.We compare the performance of the two decoupled systems with two integrated systems via simulation. For six benchmarks on 32 nodes,~phoon-O ranges from 30% to 309% slower than the best integrated system, while Typhoon-1 ranges from 13% to 132% slower. Four of the six benchmarks achieve speedups of 12 to 18 on Typhoon-O and 15 to 26 on Typhoon-1, compared with 19 to 35 on the best integrated system. Two benchmarks are hampered by high communication overheads, but selectively replacing shared-memory operations with message passing provides speedups of at least 16 on both decoupled systems. These speedups indicate that decoupled designs can potentially provide a cost-effective alternative to complex high-end DSM systems.

show abstract

A tightly-coupled processor-network interface

Cited by 10 publications

References 10 publications

Stream computations organized for reconfigurable execution

Stream computations organized for reconfigurable execution

The M-machine multicomputer

Decoupled hardware support for distributed shared memory

Contact Info

Product

Resources

About