A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States

Wu, Zhixin; Zhang, Yuejun; Du, Shimin; Guo, Zhecheng; Zhao, Wanlong

doi:10.1109/asicon52560.2021.9620275

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…Studies have also proved that replacing CMOS gates with memristors can effectively reduce circuit area and power consumption. In [11], the three-valued adder and multiplier are implemented only using memristors, in which the multiplier is implemented using only five memristors, which greatly reduces the number of components used and circuit area, and improves the operational efficiency while reducing the power consumption of the chip. Similar to [11,12] proposed a design scheme of ternary univariate logic and multiplier based on bipolar three-state memristor.…”

Section: Introductionmentioning

confidence: 99%

“…In [11], the three-valued adder and multiplier are implemented only using memristors, in which the multiplier is implemented using only five memristors, which greatly reduces the number of components used and circuit area, and improves the operational efficiency while reducing the power consumption of the chip. Similar to [11,12] proposed a design scheme of ternary univariate logic and multiplier based on bipolar three-state memristor. The results show that this scheme can effectively reduce circuit interconnection and chip area, and improve the energy efficiency of in-memory computing.…”

Section: Introductionmentioning

confidence: 99%

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A memristor crossbar based on a novel ternary memristor model

Wang,

Zhou,

Dong

et al. 2024

Nonlinear Dyn

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In this paper, a high-density programmable logic array based on a ternary memristor crossbar array is designed. Based on the three-valued state characteristics of the ternary memristor, we implement the ternary-OR logic gate and a standard ternary inverter to demonstrate the application of this proposed crossbar by using reconfigurable and programmable connections of the memristor cells in the array. Subsequently, on the basis of these logic gates, ternary NAND gates, NOR gates, XOR gates and XNOR gates are further realized. The above-mentioned logic gates all use memristance as the logic state variable. SPICE simulations are conducted to verify the functionality of the programmable gate array based on the proposed ternary memristor crossbar.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A memristor crossbar based on a novel ternary memristor model

Wang,

Zhou,

Dong

et al. 2024

Nonlinear Dyn

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show abstract

Design method for unbalanced ternary logic family based on binary memristors

Wang,

Sun,

Zhou

et al. 2024

Nonlinear Dyn

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This paper proposes a design method for unbalanced ternary logic family based on hybrid design of binary memristors and CMOS transistors, building on the foundational positive ternary logic circuits. By using the symmetry of negative and positive ternary logics, negative ternary TAND, TOR, TI, 1-3 decoder and 2-9 decoder are derived from the previously designed positive ternary basic logic gate circuits. Furthermore, negative ternary XOR, XNOR, 3-1 encoder, and 9-2 encoder are design-improved. For the first time, unbalanced ternary priority encoders is proposed, including a 3-1 priority encoder and a 9-2 priority encoderof which the former is implemented with only 7 memristors. The functionalities of these circuits are demonstrated through LTSpice simulations. Finally, hardware experiments were performed on a stable 2020 ZnO-based resistive switch array. Subsequent design of more complex digital logic circuits can benefit from this work.

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A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States

Cited by 2 publications

References 7 publications

A memristor crossbar based on a novel ternary memristor model

A memristor crossbar based on a novel ternary memristor model

Design method for unbalanced ternary logic family based on binary memristors

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