A three charge-states model for silicon nanocrystals nonvolatile memories

Transient charging current measurements and modelling in silicon nanocrystal floating gate devices

“…This hypothesis was evoked for the first time only a few years ago [11] although it is very common to measure and model this kind displacement currents in usual Flash memories [26,27]. This interpretation of the peaks in I G -V G curves was then used in other studies on nanocrystals based memories [24,28], and this behaviour was also theoretically modelled [28,29]. In this paper, we present a model which enables one to extract some structural parameters of the dot planes directly from the experimental data.…”

“…In that context, few silicon based bottom-up techniques have been investigated: annealing of a thin silicon layer deposited onto an insulator [10][11][12], low pressure chemical vapour deposition (LPCVD) of silicon clusters onto an insulator layer [13][14][15], aerosol synthesis [6,22] and thermal demixtion of a silicon rich oxide (SRO) layer. SRO may be obtained by low energy 28 Si + ions into a thermal oxide layer [16][17][18] or by CVD (chemical vapor deposition) with such parameters that a SiO X<2 layer is elaborated [19,20]. The formation of nanocrystals may imply defects at their surface or in the insulators [9].…”

Tungsten polyoxometalate molecules as active nodes for dynamic carrier exchange in hybrid molecular/semiconductor capacitors

“…All currentvoltage measurements were performed in dark at RT as well as at T ¼ 80, 100, 120 and 140 K. The voltage was applied on the top electrode and was swept from À3 V to 3 V (inversion to accumulation for the n-type Si substrate) in order to investigate the charging of POM nanoislands with electrons. 35 Fig. 11 shows typical double sweep constant ramp rate I-V curves recorded for samples A and AP for ramp rates within the range of 0.05-0.30 V/s using a fixed voltage step of 50 mV under ambient conditions.…”

Modeling and Analysis of the Charging Dynamics in Si-quantum Dots Based Non Volatile Flash Memory Cells

“…1. The structure is identical to that used by Busseret et al 4 The devices are MOS capacitors built on a p-Si substrate. The thickness of the tunnel oxide is (d fb ) 2.5nm and Si nanocrystals are obtained using a LPCVD system and are self-assembled.…”

“…We attribute these peaks to filling up of the nanocrystals with more than one electron into the quantum levels, shifted to higher energy levels due to the increase in charging energy determined by self capacitance. A model including the presence and effect of these energy levels and trap states along with the size distribution of the quantum dots is developed as an extension of the work by Busseret et al 4 The model is employed for the investigation and analysis of the charging dynamics i.e., I-t, characteristics. Results are compared with the experimental data of Ref.…”