A Thread-Level Pipeline Parallel Model for CMP

Abstract

Today, with the increasing popularity of chip multiprocessors (CMPs), the memory wall problem becomes more serious. So, making better use of the shared cache on chip is more necessary on CMP than other multiple processors architecture. In this paper, we analyze the performance of traditional special decomposed parallel implementation of red-black algorithm, and find that this parallel model does not exploit the temporary data locality of this application. Then, we restructure red-black algorithm to be a producer-consumer thread pipeline. Under this thread-level pipeline model, consumer threads can reuse the data that the former producers have fetched into the shared cache. Then the number of cache miss reduces. Our experiment results show the application performance under the thread-level pipeline parallel model achieves about 40% additional improvement on core 2. Furthermore, we propose a synchronization mechanism in hardware to support this model, and discuss the scalability of this parallel model.