Wide band gap SiC/Al 4 SiC 4 heterostructure transistor with a gate length of 5 µm is designed using a ternary carbide of Al 4 SiC 4 and its performance simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 µm gate length transistor is then laterally scaled to 2 µm and 1 µm gate length devices. The 5 µm gate length SiC/Al 4 SiC 4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 µm and 1 µm, respectively. The device breakdown voltage is 59.0 V which reduces to 31.0 V and to 18.0 V in the scaled 2 µm and the 1 µm gate length transistors. The scaled down 1 µm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm by the 5 µm gate length device.Finally, a sub-threshold slope of the scaled devices is 197.3 mV/dec, 97.6 mV/dec, and 96.1 mV/dec for gate lengths of 5 µm, 2 µm, and 1 µm, respectively.