A testability metric for path delay faults and its application

Tsai, Huan-Chih; Cheng, Kwang-Ting; Agrawal, Vishwani D.

doi:10.1145/368434.368820

Cited by 8 publications

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The procedure concatenates broadside tests, requiring fewer test cycles than the original broadside tests with the same fault coverage. The work in [11] proposes a metric which gives the testability of the circuit for path delay faults. This measure is used in scan-based Built-in Self-Test (BIST) path delay testing.…”

Section: Prior Workmentioning

confidence: 99%

At-Speed Path Delay Test

Chakraborty

Walker

2015

2015 IEEE 24th North Atlantic Test Workshop

View full text Add to dashboard Cite

This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and timeborrowing latches, that cannot be tested by any other structural test technique. The path generation algorithm uses the circuit structure, and then the paths are sequentially justified using Boolean Satisfiability algorithms.

show abstract

Section: Prior Workmentioning

confidence: 99%

At-Speed Path Delay Test

Chakraborty

Walker

2015

2015 IEEE 24th North Atlantic Test Workshop

View full text Add to dashboard Cite

show abstract

“…TPI has been explored intensively in the context of scan-based stuck-at fault approaches [32,9], but definitively less so for delay fault coverage improvement [10,22,25,31]. Traditionally, TPI targets intermediate nodes, which works well with stuck-at faults.…”

Section: Test Point Insertionmentioning

confidence: 99%

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

2011

View full text Add to dashboard Cite

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launchon-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.

show abstract

“…Another way to calculate the switching frequency is to calculate the switching probability. For a quick analysis, in our experiments, we use a probabilistic method as suggested in [17].…”

Section: Noise Weightsmentioning

confidence: 99%

Timing-Aware Power-Noise Reduction in Placement

Yeh

Merek-Sadowska

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

In this paper, we describe a placement-level decap insertion technique whose objective is to reduce power-noise, taking into account circuit timing. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells which, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors that switch infrequently, it is unlikely that this cell will suffer from a power noise problem. Based on the cell power noise estimation, we add decap padding to each cell. Then we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can allocate decaps to improve power noise, power consumption, and timing. We propose two gate-sizing algorithms. The first one uses a Sequence of Linear Programs (SLP) formulation, and the second one uses a budgeting-based heuristic algorithm. The SLP algorithm can produce better power noise results than the heuristic, at the expense of run time. Experimental results show that our techniques can effectively reduce power noise and still meet timing constraints.

show abstract

A testability metric for path delay faults and its application

Cited by 8 publications

References 13 publications

At-Speed Path Delay Test

At-Speed Path Delay Test

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Timing-Aware Power-Noise Reduction in Placement

Contact Info

Product

Resources

About