A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

“…The test devices were fabricated by a dual-gate and triple-well CMOS process with shallow trench isolation [15][16][17][18][19]. The n-wells were formed in psubstrate with deep and shallow P + -implantations, while p-wells were formed with B + -implantation.…”

“…CoSi 2 salicidation was performed to reduce resistances of both polysilicon-gates and source/drain regions. The distance between the gate edge and the source/drain electrodes was designed 1.5 µm to avoid distortion of the photoemission intensity due to the reflectance and/or interference effects of the electrodes in case of photoemission measurements [12][13][14][15][16][17][18][19]. The saturation current I S is approximated by I S =WC OX (V G -V T )v s [20], where C OX and v s are the gate capacitance and the saturation velocity, respectively.…”

“…On the other hand, as the photoemission and its intensity closely relate to the electric field near the drain region [11], the hot-carrier-induced 2-D photoemission analyses have been useful to study such 2-D hot-carrier effects along the channel-width direction [12,13] or along the channel-length direction [14][15][16][17][18]. It was reported that the photoemission intensities and the emitted photon energies were dependent on LOCOS-and trench-isolation technology [12,13].…”

A Test Structure for Spectrum Analysis of Hot-Carrier-Induced Photoemission from Scaled MOSFETs under DC and AC Operation

“…Since the hot carriers emit photons, analyses using a photoemission microscope become useful to study the high electric fields in MOSFETs [1][2][3]. Several models of hot-carrierinduced photoemission are proposed, such as recombination of hot electrons with holes generated by the impact ionization, bremsstrahlung radiation of hot carriers.…”