A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems

Cheng, Lin; Pan, Peitian; Zhao, Zhongyuan; Ranjan, Krithik; Weber, Jack; Veluri, Bandhav; Ehsani, Seyed Borna; Ruttenberg, Max; Jung, Dai Cheol; Ivanov, Preslav; Richmond, Dustin; Taylor, Michael; Zhang, Zhiru; Batten, Christopher

doi:10.1109/tcad.2021.3103825

Cited by 5 publications

(4 citation statements)

References 39 publications

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“…Since the GBI interconnection provides a memory bandwidth of 𝑛/2, we can also approximate (4) by miss concurrency supported by the GBI memory bandwidth as (6).…”

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

“…The C-AMAT given in ( 6) is smaller compared to conservative miss concurrency given in (4). The percentage deviation from (4) to (6) varies from 4 to 30 % across all cache systems. We see a higher deviation for L1-SBC system which is attributed to the fact that the miss concurrency decreases as a result of higher hit concurrency using bus cache during read cycle.…”

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

“…In recent years, many cores are trending as a on-chip computing platform [1]- [3] that can provide massive computational power for a heterogenous computing environment for big data [4] and other compute intensive embedded artificial intelligence applications [5]. Some recent work [6]- [9] on high performance computing for big data have focused on processing framework, architecture synthesis and utilization of multiple cores. With increased very large-scale integration (VLSI) density, it may be still manageable to provide heterogeneous computing using cost effective on-chip interconnection and cache memory system.…”

Section: Introductionmentioning

confidence: 99%

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An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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<p><span lang="EN-US">Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.</span></p>

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“…Since the GBI interconnection provides a memory bandwidth of 𝑛/2, we can also approximate (4) by miss concurrency supported by the GBI memory bandwidth as (6).…”

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

Section: Concurrent Average Memory Access Time (C-amat)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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“…been launched for different computing scenario applications, such as GPUs for image processing [6], [7], FPGAs for high-performance computing [8], NPUs for neural network based training [9], and DPUs for data processing [10].…”

Section: Introductionmentioning

confidence: 99%

Evolutionary Game Theory-Based Optimal Scheduling Strategy for Heterogeneous Computing

She

Zhao

2023

IEEE Access

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With the development of intelligent applications, simply relying on traditional single type of computing unit cannot efficiently satisfy diverse cloud requirements. The emergence of heterogeneous computing can efficiently achieve the adaptation of these intelligent applications by using different types of processing units such as Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA). However, the trade-off between profit and costs in the process of scheduling heterogeneous computing resources is also an issue worthy of attention. To address this challenge, this work establishes a heterogeneous computing resource scheduling model based on Stackelberg differential game, which includes three roles Computing Power Trading Platforms (CPTPs), Heterogeneous Computing Service Providers (HCSPs), and Heterogeneous Computing Application Providers (HCAPs). The objective is to maximize utility function of CPTPs and HCSPs subject to rental ratio, pricing strategy and energy consumption of resource scheduling, which has proved that there exists a Stackelberg Nash Equilibrium (NE) solution. The Support Vector Machine based on Artificial Fish (SVM-AF) is proposed to predict the access times of heterogeneous computing applications. In addition, the distributed iteration method and Cauchy distribution is adopted to optimize the computing price strategy and improve its convergence performance. The simulation results show that compared with other strategies, the proposed strategy can effectively improve computing revenue of user experience and while reducing energy consumption in the process of resource scheduling.

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