A Temporal Correlation Based Port Combination Methodology for Networks-on-Chip on Reconfigurable Systems

Wang, Daihan; Matsutani, Hiroki; Amano, Hideharu; Koibuchi, Michihiro

doi:10.1109/fpl.2007.4380676

Cited by 4 publications

(5 citation statements)

References 4 publications

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“…In this study, multiple ports with small traffic are combined in order to reduce the hardware cost. In [3], we also proposed a temporal correlation based port combination methodology for reconfigurable systems. The ports of the router can be combined so as to achieve the smallest hardware requirement.…”

Section: Related Workmentioning

confidence: 99%

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A link removal methodology for Networks-on-Chip on reconfigurable systems

Wang

Matsutani

Amano

et al. 2008

2008 International Conference on Field Programmable Logic and Applications

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While the regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

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Section: Related Workmentioning

confidence: 99%

“…Customization methods have been reported recently [2], and we also proposed a port combining method optimized to the target traffic in [3]. However, these previous researches only reduce the ports of routers, and links between routers are kept even if the amount of traffic on them is quite small.…”

Section: Introductionmentioning

confidence: 99%

A link removal methodology for Networks-on-Chip on reconfigurable systems

Wang

Matsutani

Amano

et al. 2008

2008 International Conference on Field Programmable Logic and Applications

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“…Compared with the port combination methodology [4], the link removal will achieve even more hardware savings since port combination requires extra control logic.…”

Section: Motivationmentioning

confidence: 99%

“…Moreover, this customization techniques used simply the total port bandwidth utilization as a metric for the combination without considering temporal change of the traffic. In [4], we also proposed a temporal correlation based port combination methodology for reconfigurable systems. The ports of the router can be combined so as to achieve the smallest hardware requirement.…”

Section: Related Workmentioning

confidence: 99%

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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs

Wang

Matsutani

Koibuchi

et al. 2009

IEICE Trans. Inf. & Syst.

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SUMMARYThe regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

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Multi-application Specified Link Removal Strategy for Network on Chip

Jiao

2011

2011 Fourth International Joint Conference on Computational Sciences and Optimization

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A Temporal Correlation Based Port Combination Methodology for Networks-on-Chip on Reconfigurable Systems

Cited by 4 publications

References 4 publications

A link removal methodology for Networks-on-Chip on reconfigurable systems

A link removal methodology for Networks-on-Chip on reconfigurable systems

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs

Multi-application Specified Link Removal Strategy for Network on Chip

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