A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture

Abstract

In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any specific clock tree construction, special scan cells, or scan chain reordering. Test cubes generated by any combinational ATPG can be processed by the proposed method to reduce peak and average switching activity without any capture violation. Switching activity during scan shift cycles is reduced by assigning identical values to adjacent scan inputs and switching activity during capture cycles is reduced by limiting the number of scan chains that capture responses. Hardware overhead for the proposed method is negligible. The peak transition is reduced by about 40% and average number of transitions is reduced by about 56-85%. This reduction in peak and average switching activity is achieved with no decrease in fault coverage.

Improved weight assignment for logic switching activity during at-speed test pattern generation

“…Since at-speed scan testing is being challenged by the yield loss problem [15,11], many techniques have been proposed to reduce the launch cycle SA by, for example, power-aware ATPG [12,1,2,5], X-filling [17,13,3,19], or design-fortest (DfT) [14,16]. Weighted switching activity (WSA), the summation of the switching cells' weights, e.g., fanout count plus one [8], is commonly used to assess the SA-induced IRdrop severity in ATPG for its efficiency.…”

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

“…1) can be reduced by circuit modification [9], one-hot clocking [1], or capture clock staggering [1]. However, this approach may incur significant ATPG change, test data inflation, and even fault coverage loss.…”

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing

“…Circuit-modificationbased techniques include additional circuitry insertion [5], [6], scan chain segmentation [7], scan re-ordering [8], and partial capturing [9]. On the other hand, data-manipulationbased techniques include test vector reordering [10], test generation [11], [12], and X-filling [13]- [18].…”