A systolic VLSI matrix for a family of fundamental searching problems

Halaas, Arne

doi:10.1016/s0167-9260(83)80002-9

Cited by 9 publications

(1 citation statement)

References 4 publications

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“…Pattern-Recognition Processors. There have been many proposed hardware approaches for accelerating patternmatching problems [7,11,12,15,22]. Recently, there has been been a renewed focus on accelerating patternrecognition problems using devices such as IBM's Pow-erEN Processor [13], the Titan IC RXP Regular eXpression Processor [20], and the Automata Processor (AP) [10].…”

Section: Background and Related Workmentioning

confidence: 99%

RAPID Programming of Pattern-Recognition Processors

Angstadt

Weimer

Skadron

2016

SIGARCH Comput. Archit. News

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We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct execution of non-deterministic finite automata (NFAs), and has been demonstrated to provide substantial speedup for a variety of data-processing applications. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Further, we introduce a tessellation technique for configuring the AP, which significantly reduces compile time, increases programmer productivity, and improves maintainability. We evaluate five RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by the AP. We find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact. In addition, our tessellation technique for configuring the AP has comparable device utilization to, and results in compilation that is up to four orders of magnitude faster than, current solutions.

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